# US 10,769,090 B2 · Information processing apparatus, control method of information processing, and non-transitory computer-readable storage medium for storing program > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,769,090 B2 - Document ID: US10769090B2 - Status: Granted - Kind: B2 - Application number: 16/563,991 - Filed: 2019-09-09 - Published: 2020-01-02 - Granted: 2020-09-08 - Earliest claimed: 2017-03-13 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Hidetoshi Matsumura - Web page: https://patentgrep.com/patent/US10769090B2 ## CPC - G06F 13/4068: {Electrical coupling} - G06F 7/57: Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} - G06F 9/4405: {Initialisation of multiprocessor systems} - G06F 9/4411: {Configuring for operating with peripheral devices; Loading of device drivers} - G06F 30/00: Computer-aided design [CAD] - H03K 19/177: arranged in matrix form - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An information processing apparatus includes: a programmable circuit including a plurality of reconfigurable regions in which logic is reconfigurable; and a processor coupled to the programmable circuit, the processor being configured to (a): execute an extraction process that includes extracting, from the plurality of reconfigurable regions, one or more installable regions in which any of a plurality of first circuits is installable, (b): execute a first determination process that includes determining whether each of a plurality of second circuits is installable in a first reconfigurable region, (c): execute a second determination process that includes determining a first installation circuit and a first installation region based on the determination executed by the first determination process, and (d): execute an installation process that includes installing the first installation circuit determined by the second determination process in the first installation region determined by the second determination process. ## Claims ### Claim 1 An information processing apparatus comprising: a programmable circuit including a plurality of reconfigurable regions in which logic is reconfigurable; and a processor coupled to the programmable circuit, the processor being configured to execute an extraction process that includes extracting, from the plurality of reconfigurable regions, one or more installable regions in which any of a plurality of first circuits is installable; each of the plurality of first circuits including a first processing section for executing a first process and a first input and output section for receiving and outputting information; the each of the plurality of first circuits being configured so that the positions of the first input and output sections are different from each other when each of the plurality of first circuits is installed in any of the reconfigurable regions, execute a first determination process that includes determining whether each of a plurality of second circuits is installable in a first reconfigurable region; the first reconfigurable region being adjacent to the one or more installable regions extracted by the extraction process; each of the plurality of second circuits including a second processing section for executing the first process and a second input and output section to be coupled to a first input and output section among the first input and output sections; each of the plurality of second circuits corresponding to any of the plurality of first circuits, execute a second determination process that includes determining a first installation circuit and a first installation region based on the determination executed by the first determination process; the first installation circuit being among the plurality of first circuits and to be installed in the programmable circuit; the first installation region being a region that is among the one or more installable regions and in which the first installation circuit is to be installed, and execute an installation process that includes installing the first installation circuit determined by the second determination process in the first installation region determined by the second determination process. ### Claim 2 (depends on 1) The information processing apparatus according to claim 1, wherein the second determination process is configured to determine the first installation region and the first installation circuit corresponding to a second circuit that is among the second circuits and is installable in a reserved region when a first requirement is satisfied, and wherein the first requirement is configured to be satisfied when second process processing performance of a third circuit for executing a second process is insufficient, and when a reserved region that is a reconfigurable region in which a fourth circuit for executing the second process is installable exists adjacent to a reconfigurable region in which the third circuit is installed, and when the first determination process determines that any of the plurality of second circuits is installable in the reserved region. ### Claim 3 (depends on 1) The information processing apparatus according to claim 1, wherein the second determination process is configured to determine the first installation region and the first installation circuit corresponding to a second circuit that is among the second circuits and is installable but is not installed in the reserved region when a second requirement is satisfied, and wherein the second requirement is configured to be satisfied when second process processing performance of a third circuit for executing a second process is insufficient, and when the reserved region that is a reconfigurable region in which a fourth circuit for executing the second process is installed exists adjacent to a reconfigurable region in which the third circuit is installed, and when the first determination process determines that any of the plurality of second circuits is installable in a region other than the reserved region. ### Claim 4 (depends on 2) The information processing apparatus according to claim 2, wherein the second determination process is configured to determine that the first installation circuit is installed but is not installed in the reserved region when any of the one or more installable regions extracted by the extraction process does not overlap the reserved region. ### Claim 5 (depends on 2) The information processing apparatus according to claim 2, wherein the second determination process is configured to determine that the first installation circuit is installed in a reconfigurable region including the reserved region when each of all the one or more installable regions extracted by the extraction process includes the reserved region. ### Claim 6 (depends on 1) The information processing apparatus according to claim 1, wherein the second determination process is configured to determine any of the plurality of first circuits as the first installation circuit and determine any of the one or more installable regions as the first installation region when the first determination process determines that all the second circuits are not installable in a reconfigurable region adjacent to the one or more installable regions. ### Claim 7 (depends on 1) The information processing apparatus according to claim 1, wherein the installation process is configured to install, in the programmable circuit, a second circuit, which is among the second circuits and corresponds to the first installation circuit, when first process processing performance of the first installation circuit installed in any of the one or more installable regions is insufficient, and when a reconfigurable region in which the second circuit, which is among the plurality of second circuits and corresponds to the first installation circuit, is installable exists. ### Claim 8 (depends on 1) The information processing apparatus according to claim 1, wherein the installation process is configured not to install any of the plurality of first circuits in the programmable circuit when the extraction process does not extract the installable region in which the first installation circuit is to be installed, and wherein the first process is configured to be executed by a program executed by an arithmetic processing device included in the information processing apparatus. ### Claim 9 (depends on 1) The information processing apparatus according to claim 1, wherein each of the plurality of reconfigurable regions is formed in a rectangular shape, and wherein the first input and output section of each of the plurality of first circuits is installed in one of four sides of any of the plurality of reconfigurable regions. ### Claim 10 (depends on 1) The information processing apparatus according to claim 1, further comprising: a memory configured to store configuration information of each of the plurality of first circuits and configuration information of each of the plurality of second circuits. ### Claim 11 (depends on 1) The information processing apparatus according to claim 1, wherein the number of reconfigurable regions to be used to install each of the plurality of first circuits is equal to the number of reconfigurable regions to be used to install each of the other first circuits. ### Claim 12 A control method of information processing performed by a computer having a programmable circuit including a plurality of reconfigurable regions in which logic is reconfigurable and a processor coupled to the programmable circuit, the method comprising: executing an extraction process that includes extracting, from the plurality of reconfigurable regions, one or more installable regions in which any of a plurality of first circuits is installable; each of the plurality of first circuits including a first processing section for executing a first process and a first input and output section for receiving and outputting information; the each of the plurality of first circuits being configured so that the positions of the first input and output sections are different from each other when each of the plurality of first circuits is installed in any of the reconfigurable regions, executing a first determination process that includes determining whether each of a plurality of second circuits is installable in a first reconfigurable region; the first reconfigurable region being adjacent to the one or more installable regions extracted by the extraction process; each of the plurality of second circuits including a second processing section for executing the first process and a second input and output section to be coupled to a first input and output section among the first input and output sections; each of the plurality of second circuits corresponding to any of the plurality of first circuits, executing a second determination process that includes determining a first installation circuit and a first installation region based on the determination executed by the first determination process; the first installation circuit being among the plurality of first circuits and to be installed in the programmable circuit; the first installation region being a region that is among the one or more installable regions and in which the first installation circuit is to be installed, and executing an installation process that includes installing the first installation circuit determined by the second determination process in the first installation region determined by the second determination process. ### Claim 13 A non-transitory computer-readable storage medium for storing a program which causes a computer to perform a processing, the computer having a programmable circuit including a plurality of reconfigurable regions in which logic is reconfigurable and a processor coupled to the programmable circuit, the processing comprising: executing an extraction process that includes extracting, from the plurality of reconfigurable regions, one or more installable regions in which any of a plurality of first circuits is installable; each of the plurality of first circuits including a first processing section for executing a first process and a first input and output section for receiving and outputting information; the each of the plurality of first circuits being configured so that the positions of the first input and output sections are different from each other when each of the plurality of first circuits is installed in any of the reconfigurable regions, executing a first determination process that includes determining whether each of a plurality of second circuits is installable in a first reconfigurable region; the first reconfigurable region being adjacent to the one or more installable regions extracted by the extraction process; each of the plurality of second circuits including a second processing section for executing the first process and a second input and output section to be coupled to a first input and output section among the first input and output sections; each of the plurality of second circuits corresponding to any of the plurality of first circuits, executing a second determination process that includes determining a first installation circuit and a first installation region based on the determination executed by the first determination process; the first installation circuit being among the plurality of first circuits and to be installed in the programmable circuit; the first installation region being a region that is among the one or more installable regions and in which the first installation circuit is to be installed, and executing an installation process that includes installing the first installation circuit determined by the second determination process in the first installation region determined by the second determination process.