# US 10,769,083 B2 · Source synchronized signaling mechanism

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- Number: US 10,769,083 B2
- Document ID: US10769083B2
- Status: Granted
- Kind: B2
- Application number: 16/540,477
- Filed: 2019-08-14
- Published: 2020-02-06
- Granted: 2020-09-08
- Earliest claimed: 2017-04-21
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Altug Koker; Joydeep Ray; Vasanth Ranganathan; Abhishek R. Appu
- Web page: https://patentgrep.com/patent/US10769083B2

## CPC

- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 13/4068: {Electrical coupling}
- G06F 13/42: Bus transfer protocol, e.g. handshake; Synchronisation
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An apparatus to facilitate source synchronous signaling is disclosed. The apparatus includes transfer protocol logic to provide for source synchronous transfer of data within an interconnect fabric, including one or more synchronizers having logic to a transmit data signal and a source clock (clk) signal during the transfer of data.

## Claims

### Claim 1

An apparatus comprising:
an interconnect fabric including:
a plurality of network interfaces for connection of the interconnect fabric to a plurality of nodes, each network interface including a set of one or more synchronizers, and
a plurality of network switches to route data transfers between the plurality of network interfaces;
wherein the interconnect fabric is to provide for source synchronous transfer of data within the interconnect fabric between a plurality of nodes connected to the plurality of network interfaces, the plurality of nodes including a plurality of compute nodes and a global shared memory for the plurality of compute nodes, wherein:
a first network interface of the plurality of network interfaces is to transmit a data signal and a source clock signal from a first node of the plurality of nodes, and
a second network interface of the plurality of network interfaces is to receive the data signal and the source clock signal for a second node of the plurality of nodes, wherein the second network interface is to sample and filter the data signal based on a clock domain associated with the source clock signal.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first and second network interfaces are to provide for an asynchronous transfer of data with balanced sampling requirements.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein each compute node of the plurality of compute nodes includes one or more graphics processing cores.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the data signal is at least a portion of one or more frames of graphics data.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the data signal is to be transmitted on a first path from the first network interface to the second network interface through the interconnect fabric, and the source clock signal is to be transmitted on a second path from the first network interface to the second network interface through the interconnect fabric.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the plurality of network switches includes a plurality of crossbar switches.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein each network switch includes a plurality of ports to receive and transmit data and a buffer to queue data received at the network switch, and wherein each network switch is to control routing of data via the network switch.

### Claim 8

A system comprising:
a plurality of compute nodes;
a global shared memory for the plurality of compute nodes; and
an interconnect fabric including:
a plurality of network interfaces for connection of the interconnect fabric to a plurality of nodes, the plurality of nodes including the plurality of compute nodes and the global shared memory, each network interface including a set of one or more synchronizers, and
a plurality of network switches to route data transfers between the plurality of network interfaces;
wherein the interconnect fabric is to provide for source synchronous transfer of data within the interconnect fabric between the plurality of nodes, wherein:
a first network interface of the plurality of network interfaces is to transmit a data signal and a source clock signal from a first node of the plurality of nodes, and
a second network interface of the plurality of network interfaces is to receive the data signal and the source clock signal for a second node of the plurality of nodes, wherein the second network interface is to sample and filter the data signal based on a clock domain associated with the source clock signal.

### Claim 9 (depends on 8)

The system of claim 8, wherein the first and second network interfaces are to provide for an asynchronous transfer of data with balanced sampling requirements.

### Claim 10 (depends on 8)

The system of claim 8, wherein each compute node of the plurality of compute nodes includes one or more graphics processing cores.

### Claim 11 (depends on 8)

The system of claim 8, wherein the data signal is at least a portion of one or more frames of graphics data.

### Claim 12 (depends on 8)

The system of claim 8, wherein the data signal is to be transmitted on a first path from the first network interface to the second network interface through the interconnect fabric, and the source clock signal is to be transmitted on a second path from the first network interface to the second network interface through the interconnect fabric.

### Claim 13 (depends on 8)

The system of claim 8, wherein the plurality of network switches includes a plurality of crossbar switches.

### Claim 14 (depends on 13)

The system of claim 13, wherein each network switch includes a plurality of ports to receive and transmit data and a buffer to queue data received at the network switch, and wherein each network switch is to control routing of data via the network switch.

### Claim 15

A method comprising:
receiving a data signal and a source clock signal from a first node of a plurality of nodes at a first network interface of an interconnect fabric;
transmitting the data signal and the source clock signal across the interconnect fabric;
receiving the data signal and the source clock signal at a second network interface for a second node of the plurality of nodes; and
sampling and filtering the data signal at the second network interface based on a clock domain associated with the source clock signal, wherein the interconnect fabric to provide for source synchronous transfer of the data signal within the interconnect fabric;
wherein the plurality of nodes includes a plurality of compute nodes and a global shared memory, and wherein each of the first network interface and second network interface include a set of one or more synchronizers.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
providing, by the first and second network interfaces, an asynchronous transfer of data with balanced sampling requirements.

### Claim 17 (depends on 15)

The method of claim 15, wherein each compute node of the plurality of compute nodes includes one or more graphics processing cores.

### Claim 18 (depends on 15)

The method of claim 15, wherein transmitting the data signal includes transmitting one or more frames of graphics data.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
transmitting the data signal on a first path from the first network interface to the second network interface through the interconnect fabric; and
transmitting the source clock signal on a second path from the first network interface to the second network interface through the interconnect fabric.