# US 10,769,073 B2 · Bandwidth-based selective memory channel connectivity on a system on chip

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- Number: US 10,769,073 B2
- Document ID: US10769073B2
- Status: Granted
- Kind: B2
- Application number: 15/939,031
- Filed: 2018-03-28
- Published: 2019-10-03
- Granted: 2020-09-08
- Earliest claimed: 2018-03-28
- Assignees: QUALCOMM Incorporated
- Applicants: Qualcomm Incorporated
- Inventors: Kunal Desai; Satyaki Mukherjee; Siddharth Kamdar; Abhinav Mittal; Vinayak Shrivastava
- Web page: https://patentgrep.com/patent/US10769073B2

## CPC

- G06F 12/10: Address translation
- G06F 13/1684: {using multiple buses}
- G06F 3/0646: {Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems, methods, and computer programs are disclosed for managing memory channel connectivity. One embodiment of a system comprises a high-bandwidth memory client, a low-bandwidth memory client, and an address translator. The high-bandwidth memory client is electrically coupled to each of a plurality of memory channels via an interconnect. The low-bandwidth memory client is electrically coupled to only a portion of the plurality of memory channels via the interconnect. The address translator is in communication with the high-bandwidth memory client and configured to perform physical address manipulation when a memory page to be accessed by the high-bandwidth memory client is shared with the low-bandwidth memory client.

## Claims

### Claim 1

A system for managing memory channel connectivity, the system comprising:
a high-bandwidth memory client electrically coupled to each of a plurality of memory channels via an interconnect;
a low-bandwidth memory client electrically coupled to only a portion of the plurality of memory channels via the interconnect; and
an address translator in communication with the high-bandwidth memory client and configured to perform physical address manipulation when a memory page to be accessed by the high-bandwidth memory client is shared with the low-bandwidth memory client.

### Claim 2 (depends on 1)

The system of claim 1, wherein the address translator is further configured to:
receive, from a memory management unit coupled to the high-bandwidth memory client, an incoming physical address associated with the memory page shared between the high-bandwidth memory client and the low-bandwidth memory client; and
translate the incoming physical address to a translated physical address.

### Claim 3 (depends on 2)

The system of claim 2, wherein the translated physical address diverts memory traffic to only the portion of the plurality of memory channels to which the low-bandwidth memory client is electrically coupled.

### Claim 4 (depends on 2)

The system of claim 2, wherein the interconnect comprises a memory network on chip comprising:
a first initiator network interface unit associated with the high-bandwidth memory client;
a second initiator network interface unit associated with the low-bandwidth memory client; and
a plurality of target network interface units coupled to each of the plurality of memory channels.

### Claim 5 (depends on 1)

The system of claim 1, wherein the address translator in communication with the high-bandwidth memory client is configured to disable physical address manipulation when the memory page is not being shared between the high-bandwidth memory client and the low-bandwidth memory client.

### Claim 6 (depends on 1)

The system on chip of claim 1, wherein the address translator modifies an incoming physical address based on page based hardware attributes (PBHA) associated with the memory page shared between the high-bandwidth memory client and the low-bandwidth memory client.

### Claim 7 (depends on 6)

The system on chip of claim 6, wherein the PBHA specifies the portion of the plurality of memory channels to which the low-bandwidth memory client is electrically coupled.

### Claim 8 (depends on 1)

The system on chip of claim 1, wherein the high-bandwidth memory client comprises one of a central processing unit (CPU) and a graphics processing unit (GPU) and the low-bandwidth memory client comprises digital signal processor (DSP).

### Claim 9

A method for managing memory channel connectivity on a system on chip (SoC), the method comprising:
connecting a first memory client on a system on chip (SoC) to each of a plurality of memory channels;
connecting a second memory client on the SoC to only a portion of the plurality of memory channels;
the first memory client initiating a memory transaction involving shared memory with the second memory client;
receiving a physical address for the memory transaction; and
translating the physical address to divert memory traffic to only the portion of the plurality of memory channels to which the second memory client is connected.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first memory client comprises a high-performance processing device and the second memory client comprises a low-performance processing device.

### Claim 11 (depends on 9)

The method of claim 9, wherein the shared memory comprises one or more shared pages.

### Claim 12 (depends on 11)

The method of claim 11, wherein the receiving the physical address for the memory transaction comprises:
determining one or more descriptors in a page table that specify the portion of the plurality of memory channels to which the second memory client is connected.

### Claim 13 (depends on 12)

The method of claim 12, wherein the one or more descriptors comprise upper attributes of the page table.

### Claim 14 (depends on 9)

The method of claim 9, wherein the plurality of memory channels comprise double data rate (DDR) channels in communication with a dynamic random access memory.

### Claim 15 (depends on 9)

The method of claim 9, wherein the physical address for the memory transaction is received from a memory management unit.

### Claim 16

A system for managing memory channel connectivity on a system on chip (SoC), the system comprising:
means for connecting a first memory client on a system on chip (SoC) to each of a plurality of memory channels and a second memory client on the SoC to only a portion of the plurality of memory channels;
means for receiving a physical address for a memory transaction generated by the first memory client and involving a shared page with the second memory client; and
means for translating the physical address to divert memory traffic to only the portion of the plurality of memory channels to which the second memory client is connected.

### Claim 17 (depends on 16)

The system of claim 16, wherein the means for connecting comprises a memory interconnect.

### Claim 18 (depends on 16)

The system of claim 16, wherein the means for connecting comprises a memory network on chip.

### Claim 19 (depends on 16)

The system of claim 16, wherein the means for receiving the physical address for the memory transaction comprises a memory management unit.

### Claim 20 (depends on 16)

The system of claim 16, wherein the means for translating the physical address comprises an address translator coupled to a memory management unit and a memory network on chip.

### Claim 21 (depends on 16)

The system of claim 16, wherein the first memory client comprises a high-performance processing device and the second memory client comprises a low-performance processing device.

### Claim 22 (depends on 16)

The system of claim 16, wherein the plurality of memory channels comprise double data rate (DDR) channels in communication with a dynamic random access memory.

### Claim 23 (depends on 16)

The system of claim 16, wherein the means for translating the physical address comprises:
means for determining one or more descriptors in a page table that specify the portion of the plurality of memory clients to which the second memory client is connected.

### Claim 24 (depends on 23)

The system of claim 23, wherein the one or more descriptors comprise upper attributes of the page table.

### Claim 25

A computer program embodied in a non-transitory computer readable medium and executed by a processor, the computer program for managing memory channel connectivity on a system on chip (SoC) comprising a first memory client and a second memory client, the computer program comprising logic configured to:
receive a physical address for a memory transaction generated by the first memory client and involving a shared page with the second memory client, the first memory client connected to each of a plurality of memory channels and the second memory client connected to only a portion of the plurality of memory channels;
determine one or more descriptors in a page table for the shared page that specify the portion of the plurality of memory channels to which the second memory client is connected; and
modify the physical address to divert memory traffic to only the portion of the plurality of memory channels to which the second memory client is connected.

### Claim 26 (depends on 25)

The computer program of claim 25, wherein the one or more descriptors comprise upper attributes of the page table.

### Claim 27 (depends on 25)

The computer program of claim 25, wherein the first memory client comprises a high-performance processing device and the second memory client comprises a low-performance processing device.

### Claim 28 (depends on 25)

The computer program of claim 25, wherein the physical address is received from a memory management unit.

### Claim 29 (depends on 25)

The computer program of claim 25, wherein the plurality of memory channels comprise double data rate (DDR) channels in communication with a dynamic random access memory.

### Claim 30 (depends on 25)

The computer program of claim 25, wherein the first memory client comprises one of a central processing unit and a graphics processing unit and the second memory client comprises a digital signal processor.