# US 10,769,072 B2 · Avoid cache lookup for cold cache

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,769,072 B2
- Document ID: US10769072B2
- Status: Granted
- Kind: B2
- Application number: 16/277,114
- Filed: 2019-02-15
- Published: 2019-08-15
- Granted: 2020-09-08
- Earliest claimed: 2017-04-17
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Abhishek R. Appu; Altug Koker; Joydeep Ray; Prasoonkumar Surti; Kamal Sinha; Kiran C. Veernapu; Balaji Vembu
- Web page: https://patentgrep.com/patent/US10769072B2

## CPC

- G06F 12/0888: using selective caching, e.g. bypass
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06T 1/60: Memory management
- G06F 2212/1024: Latency reduction
- G06F 2212/1028: Power efficiency
- G06F 2212/6032: Way prediction in set-associative cache
- G06F 2213/0026: PCI express
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive, in a read/modify/write (RMW) pipeline, a cache access request from a requestor, wherein the cache request comprises a cache set identifier associated with requested data in the cache set, determine whether the cache set associated with the cache set identifier is in an inaccessible invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to terminate the cache access request. Other embodiments are also disclosed and claimed.

## Claims

### Claim 1

A general purpose graphics processor comprising:
an instruction cache to receive graphics processing instructions;
a general-purpose graphics processing compute block comprising a plurality of graphics processing cores to perform operations to execute the graphics processing instructions;
a cache memory communicatively coupled to at least one of the plurality of graphics processing cores; and
a processor to:
receive a cache access request from at least one of the plurality of graphics processing cores, wherein the cache access request comprises a cache set identifier associated with requested data in a cache set; and
terminate the cache access request in response to a determination that the cache set associated with the cache set identifier is in an inaccessible state or an invalid state and that a read-modify-write (RMW) pipeline is empty or includes only read accesses.

### Claim 2 (depends on 1)

The general purpose graphics processor of claim 1, the processor to:
retrieve a cache state tag associated with the cache set; and
determine a value of the cache state tag.

### Claim 3 (depends on 2)

The general purpose graphics processor of claim 2, the processor to determine whether the cache set is in at least one of a cold state or an invalid state.

### Claim 4 (depends on 1)

The general purpose graphics processor of claim 1, the processor to:
launch a memory access request for the requested data from a memory module coupled to the cache.

### Claim 5 (depends on 4)

The general purpose graphics processor of claim 4, the processor to:
return the requested data to the requestor.

### Claim 6

An electronic device, comprising:
a general purpose graphics processor, comprising:
an instruction cache to receive graphics processing instructions;
a general-purpose graphics processing compute block comprising a plurality of graphics processing cores to perform operations to execute the graphics processing instructions;
a cache memory communicatively coupled to at least one of the plurality of graphics processing cores; and
a processor having one or more processor cores, the processor to:
receive a cache access request from at least one of the plurality of graphics processing cores, wherein the cache access request comprises a cache set identifier associated with requested data in a cache set; and
terminate the cache access request in response to a determination that the cache set associated with the cache set identifier is in an inaccessible state or an invalid state and that a read-modify-write (RMW) pipeline is empty or includes only read accesses; and
a computer readable memory communicatively coupled to the processor.

### Claim 7 (depends on 6)

The electronic device of claim 6, the processor to:
retrieve a cache state tag associated with the cache set; and
determine a value of the cache state tag.

### Claim 8 (depends on 7)

The electronic device of claim 7, the processor to determine whether the cache set is in at least one of a cold state or an invalid state.

### Claim 9 (depends on 6)

The electronic device of claim 6, the processor to:
launch a memory access request for the requested data from a memory module coupled to the cache.

### Claim 10 (depends on 9)

The electronic device of claim 9, the processor to:
return the requested data to the requestor.

### Claim 11

A method comprising:
receiving a cache access request from at least one of a plurality of graphics processing cores, wherein the cache access request comprises a cache set identifier associated with requested data in a cache set; and
terminating the cache access request in response to a determination that the cache set associated with the cache set identifier is in an inaccessible state or an invalid state and that a read-modify-write (RMW) pipeline is empty or includes only read accesses.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
retrieving a cache state tag associated with the cache set; and
determining a value of the cache state tag.

### Claim 13 (depends on 12)

The method of claim 12, further comprising determining whether the cache set is in at least one of a cold state or an invalid state.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
launching a memory access request for the requested data from a memory module coupled to the cache.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
returning the requested data to the requestor.

### Claim 16

One or more non-transitory computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:
receive a cache access request from at least one of a plurality of graphics processing cores, wherein the cache access request comprises a cache set identifier associated with requested data in a cache set; and
terminate the cache access request in response to a determination that the cache set associated with the cache set identifier is in an inaccessible state or an invalid state and that a read-modify-write (RMW) pipeline is empty or includes only read accesses.

### Claim 17 (depends on 16)

The non-transitory computer-readable medium of claim 16, comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
retrieve a cache state tag associated with the cache set; and
determine a value of the cache state tag.

### Claim 18 (depends on 17)

The non-transitory computer-readable medium of claim 17, comprising one or more instructions that when executed on the at least one processor configure the at least one processor to determine whether the cache set is in at least one of a cold state or an invalid state.

### Claim 19 (depends on 16)

The non-transitory computer-readable medium of claim 16, comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
launch a memory access request for the requested data from a memory module coupled to the cache.

### Claim 20 (depends on 19)

The non-transitory computer-readable medium of claim 19, comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
return the requested data to the requestor.