# US 10,769,071 B2 · Coherent memory access

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- Number: US 10,769,071 B2
- Document ID: US10769071B2
- Status: Granted
- Kind: B2
- Application number: 16/156,654
- Filed: 2018-10-10
- Published: 2020-04-16
- Granted: 2020-09-08
- Earliest claimed: 2018-10-10
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Timothy P. Finkbeiner; Troy D. Larsen
- Web page: https://patentgrep.com/patent/US10769071B2

## CPC

- G06F 12/0815: Cache consistency protocols
- G06F 12/0877: Cache access modes
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 2212/221: Static RAM
- G06F 2212/656: Address space sharing
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. Coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address.

## Claims

### Claim 1

An apparatus, comprising:
a memory array;
a first processing resource;
a first cache line and a second cache line coupled to the memory array;
a first cache controller coupled to the first processing resource and to the first cache line and configured to provide coherent access to data stored in the second cache line and corresponding to a memory address; and
a second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line and configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address,
wherein coherent access is provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address, and
wherein coherent access is provided by, responsive to determining that the memory address is stored in the second cache line address register, locking the second cache line prior to copying the data from the second cache line to the first cache line.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the apparatus is a bank of a memory system.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the first processing resource is a bank controller.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the first cache controller and the second cache controller are further configured to provide coherent access to the data responsive to receiving a read access command and a write access command.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the second cache controller is coupled to the second processing resource through a stream interconnect.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the second processing resource is an application processing resource.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the second cache controller is coupled to the second processing resource through a host interface.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the second processing resource is a central processing unit (CPU).

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the first cache controller and the second cache controller are further configured to provide coherent access to the data via a direct coupling between the first cache controller and the second cache controller.

### Claim 10

A method for providing coherent data, comprising:
receiving, at a first cache controller, a read access command requesting data from a memory address;
determining whether the memory address is associated with a first cache line corresponding to the first cache controller by referencing a first cache line address register;
responsive to determining that the memory address is not associated with the first cache line, determining whether the memory address is associated with a second cache line corresponding to a second cache controller by referencing a second cache line address register;
responsive to determining that the memory address is associated with the second cache line by determining whether the memory address is stored in the second cache line address register corresponding to the second cache controller:
responsive to determining that the memory address is stored in the second cache line address register, locking the second cache line;
copying the requested data from the second cache line to the first cache line to provide data coherency between the first cache line and the second cache line; and
responding to the read access command by providing the requested data stored in the first cache line.

### Claim 11 (depends on 10)

The method of claim 10, wherein the read access command includes the memory address of the requested data.

### Claim 12 (depends on 11)

The method of claim 11, wherein determining whether the memory address is associated with the first cache line further comprises determining whether a value stored in the first cache line address register of the first cache controller is equal to the memory address.

### Claim 13 (depends on 12)

The method of claim 12, wherein responsive to determining that the value stored in the first registers is equal to the memory address, responding to the read access command by providing the requested data stored in the first cache line.

### Claim 14 (depends on 10)

The method of claim 10, wherein responsive to determining that the first cache line is populated, flushing the first cache line or writing the first cache line to a memory array coupled to the first cache line and the second cache line.

### Claim 15 (depends on 10)

The method of claim 10, wherein responsive to locking the second cache line, requesting a copying of the requested data stored in the second cache line from an abstract state machine (ASM), wherein the copying is a direct transfer of the requested data from the second cache line to the first cache line.

### Claim 16 (depends on 10)

The method of claim 10, wherein responsive to transferring the requested data to the first cache line, unlocking the second cache line.

### Claim 17

A method for data coherency, comprising:
receiving a write access command having a memory address and a first data to be written, wherein the write access command is received at a first cache controller of a memory device;
determining whether the memory address is associated with a first cache line corresponding to the first cache controller by referencing a first cache line address register of the first cache controller;
responsive to determining that the memory address is not associated with the first cache line, determining whether the memory address is associated with a second cache line corresponding to a second cache controller by referencing a second cache line address register of the second cache controller;
responsive to determining that the memory address is associated with the second cache line:
copying a second data stored in the second cache line to the first cache line to provide data coherency between the first cache line and the second cache line; and
writing the first data to the first cache line.

### Claim 18 (depends on 17)

The method of claim 17, wherein responsive to determining that the memory address is associated with the first cache line, storing the first data in the first cache line.

### Claim 19 (depends on 18)

The method of claim 18, wherein responsive to determining that the memory address is associated with the first cache line, determining whether the second cache line corresponding to the second cache controller is also associated with the memory address.

### Claim 20 (depends on 19)

The method of claim 19, wherein responsive to determining that the memory address is associated with the second cache controller, providing an invalidation command to the second cache controller to invalidate the second cache line.

### Claim 21

A memory system, comprising:
a first bank comprising a first bank controller;
a second bank coupled to the first bank and comprising:
a second bank controller;
a first cache controller, coupled to the first bank controller, and configured to provide data coherency to a first cache line and a second cache line, with a second data stored in the second cache line, responsive to receiving a first access command from the first bank controller, wherein the first cache line is associated with the first cache controller;
a second cache controller coupled to the second bank controller and the first cache controller and configured to provide data coherency to the first cache line and the second cache line with a first data stored in the first cache line responsive to receiving a second access command from the second bank controller, wherein the second cache line is associated with the second cache controller.

### Claim 22 (depends on 21)

The memory system of claim 21, wherein the first cache controller is coupled to the first bank controller through an interconnect interface.

### Claim 23 (depends on 22)

The memory system of claim 22, wherein the interconnect interface transfers a stream of data.

### Claim 24 (depends on 23)

The memory system of claim 23, wherein the interconnect interface functions independent of timing limitations.