# US 10,769,068 B2 · Concurrent modification of shared cache line by multiple processors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,769,068 B2 - Document ID: US10769068B2 - Status: Granted - Kind: B2 - Application number: 15/809,049 - Filed: 2017-11-10 - Published: 2019-05-16 - Granted: 2020-09-08 - Earliest claimed: 2017-11-10 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Nicholas C. Matsakis; Craig R. Walters; Jane H. Bartik; Chung-Lung K. Shum; Elpida Tzortzatos - Web page: https://patentgrep.com/patent/US10769068B2 ## CPC - G06F 12/0817: using directory methods - G06F 12/084: with a shared cache - G06F 2212/1024: Latency reduction - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non-Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data. ## Claims ### Claim 1 A computer program product for facilitating processing within a computing environment, the computer program product comprising: at least one computer readable storage medium readable by at least one processing circuit and storing instructions for performing a method comprising: obtaining, from a plurality of processors of the computing environment, a plurality of store requests to store to a shared cache line, the plurality of store requests being of a concurrent store type in which non-exclusive access to the shared cache line for storing data by the plurality of processors is being requested; and storing concurrently, based on the plurality of store requests, data to the shared cache line, wherein the plurality of processors concurrently maintain write access to the shared cache line, and wherein the storing concurrently comprises storing the data directly to the shared cache line absent storing the data in one or more private caches of the plurality of processors and absent inspection by the plurality of processors of content within the shared cache line being updated by the data. ### Claim 2 (depends on 1) The computer program product of claim 1, wherein the method further comprises setting a cache directory state associated with the shared cache line to shared-modifiable indicating multiple store requests by multiple processors are permissible. ### Claim 3 (depends on 1) The computer program product of claim 1, wherein the data comprises an update to a global shared-modifiable structure maintained in the shared cache line. ### Claim 4 (depends on 1) The computer program product of claim 1, wherein the storing concurrently the data is performed absent sending a cross-invalidate to the plurality of processors. ### Claim 5 (depends on 1) The computer program product of claim 1, wherein the method further comprises: obtaining a fetch request requesting access to the shared cache line, the fetch request being different from the concurrent store type; performing serialization for the shared cache line based on the fetch request; and reading the data from the shared cache line, based on completing the serialization. ### Claim 6 (depends on 5) The computer program product of claim 5, wherein the performing serialization comprises: stopping outstanding stores to the shared cache line; and synchronizing data of the shared cache line. ### Claim 7 (depends on 5) The computer program product of claim 5, wherein the method further comprises changing ownership state of the shared cache line, based on the fetch request, from shared-modifiable to another state. ### Claim 8 (depends on 7) The computer program product of claim 7, wherein the other state is exclusive or read-only, based on the fetch request. ### Claim 9 (depends on 1) The computer program product of claim 1, wherein the obtaining the plurality of store requests comprises receiving a plurality of fetch due to non-coherent store requests from the plurality of processors, the plurality of fetch due to non-coherent store requests being architecturally defined to allow non-blocking modifications to the shared cache line. ### Claim 10 (depends on 1) The computer program product of claim 1, wherein the storing concurrently the data to the shared cache line comprises updating a shared counter of the shared cache line without knowing a value of the shared counter at a time of the storing. ### Claim 11 A computer system for facilitating processing within a computing environment, the computer system comprising: a memory; and at least one processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising: obtaining, from a plurality of processors of the computing environment, a plurality of store requests to store to a shared cache line, the plurality of store requests being of a concurrent store type in which non-exclusive access to the shared cache line for storing data by the plurality of processors is being requested; and storing concurrently, based on the plurality of store requests, data to the shared cache line, wherein the plurality of processors concurrently maintain write access to the shared cache line, and wherein the storing concurrently comprises storing the data directly to the shared cache line absent storing the data in one or more private caches of the plurality of processors and absent inspection by the plurality of processors of content within the shared cache line being updated by the data. ### Claim 12 (depends on 11) The computer system of claim 11, wherein the method further comprises setting a cache directory state associated with the shared cache line to shared-modifiable indicating multiple store requests by multiple processors are permissible. ### Claim 13 (depends on 11) The computer system of claim 11, wherein the method further comprises: obtaining a fetch request requesting access to the shared cache line, the fetch request being different from the concurrent store type; performing serialization for the shared cache line based on the fetch request; and reading the data from the shared cache line, based on completing the serialization. ### Claim 14 (depends on 11) The computer system of claim 11, wherein the obtaining the plurality of store requests comprises receiving a plurality of fetch due to non-coherent store requests from the plurality of processors, the plurality of fetch due to non-coherent store requests being architecturally defined to allow non-blocking modifications to the shared cache line. ### Claim 15 (depends on 11) The computer system of claim 11, wherein the storing concurrently the data to the shared cache line comprises updating a shared counter of the shared cache line without knowing a value of the shared counter at a time of the storing. ### Claim 16 A computer-implemented method of facilitating processing within a computing environment, the computer-implemented method comprising: obtaining, from a plurality of processors of the computing environment, a plurality of store requests to store to a shared cache line, the plurality of store requests being of a concurrent store type in which non-exclusive access to the shared cache line for storing data by the plurality of processors is being requested; and storing concurrently, based on the plurality of store requests, data to the shared cache line, wherein the plurality of processors concurrently maintain write access to the shared cache line, and wherein the storing concurrently comprises storing the data directly to the shared cache line absent storing the data in one or more private caches of the plurality of processors and absent inspection by the plurality of processors of content within the shared cache line being updated by the data. ### Claim 17 (depends on 16) The computer-implemented method of claim 16, further comprising setting a cache directory state associated with the shared cache line to shared-modifiable indicating multiple store requests by multiple processors are permissible. ### Claim 18 (depends on 16) The computer-implemented method of claim 16, further comprising: obtaining a fetch request requesting access to the shared cache line, the fetch request being different from the concurrent store type; performing serialization for the shared cache line based on the fetch request; and reading the data from the shared cache line, based on completing the serialization. ### Claim 19 (depends on 16) The computer-implemented method of claim 16, wherein the obtaining the plurality of store requests comprises receiving a plurality of fetch due to non-coherent store requests from the plurality of processors, the plurality of fetch due to non-coherent store requests being architecturally defined to allow non-blocking modifications to the shared cache line. ### Claim 20 (depends on 16) The computer-implemented method of claim 16, wherein the storing concurrently the data to the shared cache line comprises updating a shared counter of the shared cache line without knowing a value of the shared counter at a time of the storing.