# US 10,768,989 B2 · Virtual vector processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,768,989 B2 - Document ID: US10768989B2 - Status: Granted - Kind: B2 - Application number: 15/872,762 - Filed: 2018-01-16 - Published: 2019-01-24 - Granted: 2020-09-08 - Earliest claimed: 2006-03-22 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Anthony Nguyen; Engin Ipek; Victor Lee; Daehyun Kim; Mikhail Smelyanskiy - Web page: https://patentgrep.com/patent/US10768989B2 ## CPC - G06F 9/5044: {considering hardware capabilities} - G06F 15/8053: {Vector processors} - G06F 2209/509: Offload - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution. ## Claims ### Claim 1 An apparatus comprising: a first logic circuitry to allocate a first portion of one or more operations corresponding to a virtual vector request to a first processor core; and a second logic circuitry to generate a first signal corresponding to a second portion of the one or more operations. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising a second processor core to receive the first signal, wherein the second processor core comprises: a third logic circuitry to allocate a third portion of the one or more operations to the second processor core; and a fourth logic circuitry to generate a second signal corresponding to a fourth portion of the one or more operations. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the third logic circuitry is to allocate the third portion based on information corresponding to one or more available resources of the second processor core. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein the third logic circuitry is to allocate the third portion based on information corresponding to the first signal. ### Claim 5 (depends on 2) The apparatus of claim 2, further comprising a fourth logic circuitry to maintain information corresponding to one or more available resources of the second processor core. ### Claim 6 (depends on 2) The apparatus of claim 2, wherein the third logic circuitry is to allocate the third portion based on overhead information corresponding to communication with one or more of the first processor core or a third processor core. ### Claim 7 (depends on 2) The apparatus of claim 2, further comprising a fifth logic circuitry to transmit an acknowledgment signal to the first processor core after the second processor core has retired one or more operations corresponding to the third portion. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the first processor core comprises one or more of the first logic circuitry or the second logic circuitry. ### Claim 9 (depends on 1) The apparatus of claim 1, further comprising a plurality of processor cores. ### Claim 10 (depends on 1) The apparatus of claim 1, further comprising a third logic circuitry to maintain information corresponding to one or more available resources of the first processor core. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the first logic circuitry is to allocate the first portion based on information corresponding to one or more available resources of the first processor core. ### Claim 12 (depends on 1) The apparatus of claim 1, further comprising a second processor core to generate a second signal, wherein the first logic circuitry is to allocate the first portion based on information corresponding to the second signal. ### Claim 13 (depends on 1) The apparatus of claim 1, further comprising a third logic circuitry is to schedule one or more tasks corresponding to the first portion. ### Claim 14 (depends on 1) The apparatus of claim 1, wherein the first logic circuitry is to allocate the first portion based on overhead information corresponding to communication with a second processor core. ### Claim 15 (depends on 1) The apparatus of claim 1, further comprising a memory to store one or more instructions corresponding to the virtual vector request. ### Claim 16 (depends on 1) The apparatus of claim 1, further comprising a third logic circuitry to aggregate a first computational result corresponding to the first portion and a second computational result corresponding to the second portion. ### Claim 17 (depends on 1) The apparatus of claim 1, wherein the first signal comprises data corresponding to one or more of an identifier of the first processor core, a starting value corresponding to the second portion, or an end value corresponding to the second portion. ### Claim 18 A method comprising: executing a first set of operations corresponding to a virtual vector instruction on a first processor; generating a first signal corresponding to a second set of operations of the virtual vector instruction; and executing at least a portion of the second set of operations on a second processor. ### Claim 19 (depends on 18) The method of claim 18, further comprising allocating the first set of operations based on information corresponding to one or more available resources of the first processor. ### Claim 20 (depends on 18) The method of claim 18, further comprising maintaining information corresponding to one or more available resources of one or more of the first processor or the second processor. ### Claim 21 (depends on 18) The method of claim 18, further comprising allocating the first set of operations based on overhead information corresponding to communication between the first processor and the second processor. ### Claim 22 (depends on 18) The method of claim 18, further comprising transmitting an acknowledgment signal to the first processor after the second processor has retired one or more operations corresponding to the second set of operations.