# US 10,768,936 B2 · Block-based processor including topology and control registers to indicate resource sharing and size of logical processor

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- Number: US 10,768,936 B2
- Document ID: US10768936B2
- Status: Granted
- Kind: B2
- Application number: 14/998,146
- Filed: 2015-12-23
- Published: 2017-03-23
- Granted: 2020-09-08
- Earliest claimed: 2015-09-19
- Assignees: Microsoft Technology Licensing, LLC
- Applicants: Microsoft Technology Licensing, LLC
- Inventors: Douglas C. Burger; Aaron L. Smith
- Web page: https://patentgrep.com/patent/US10768936B2

## CPC

- G06F 9/3016: {Decoding the operand specifier, e.g. specifier format}
- G06F 9/268: {Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs}
- G06F 9/30007: {to perform operations on data operands}
- G06F 9/30021: {Compare instructions, e.g. Greater-Than, Equal-To, MINMAX}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/3004: {to perform operations on memory}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/3005: {to perform operations for flow control}
- G06F 9/30058: {Conditional branch instructions}
- G06F 9/30072: {to perform conditional operations, e.g. using predicates or guards}
- G06F 9/30076: {to perform miscellaneous control operations, e.g. NOP}
- G06F 9/30087: {Synchronisation or serialisation instructions}
- G06F 9/3009: {Thread control instructions}
- G06F 9/30098: {Register arrangements}
- G06F 9/30101: {Special purpose registers}
- G06F 9/30105: {Register structure}
- G06F 9/30138: {Extension of register space, e.g. register cache}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/30167: {of immediate specifier, e.g. constants}
- G06F 9/30189: {according to execution mode, e.g. mode flag}
- G06F 9/32: Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence)
- G06F 9/323: {for indirect branch instructions}
- G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)}
- G06F 9/35: Indirect addressing
- G06F 9/3802: {Instruction prefetching}
- G06F 9/3804: {for branches, e.g. hedging, branch folding}
- G06F 9/3822: {Parallel decoding, e.g. parallel decode units}
- G06F 9/3824: {Operand accessing}
- G06F 9/3828: {with global bypass, e.g. between pipelines, between clusters}
- G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding}
- G06F 9/3842: {Speculative instruction execution}
- G06F 9/3848: {using hybrid branch prediction, e.g. selection between prediction techniques}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3853: {of compound instructions}
- G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating}
- G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags}
- G06F 9/3858: {Result writeback, i.e. updating the architectural state or memory}
- G06F 9/38585: {with result invalidation, e.g. nullification}
- G06F 9/3867: {using instruction pipelines}
- G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel}
- G06F 9/3891: {organised in groups of units sharing resources, e.g. clusters}
- G06F 9/466: {Transaction processing}
- G06F 9/528: {by using speculative mechanisms}
- G06F 11/36: Prevention of errors by analysis, debugging or testing of software
- G06F 11/3648: {using additional hardware}
- G06F 11/3656: {using a specific debug interface}
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 12/0862: with prefetch
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G06F 15/7867: {with reconfigurable architecture}
- G06F 15/80: comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15})
- G06F 15/8007: {single instruction multiple data [SIMD] multiprocessors}
- G06F 9/3013: {according to data content, e.g. floating-point registers, address registers}
- G06F 9/321: {Program or instruction counter, e.g. incrementing}
- G06F 9/355: Indexed addressing
- G06F 9/3557: {using program counter as base address}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 2212/452: Instruction code
- G06F 2212/602: Details relating to cache prefetching
- G06F 2212/604: Details relating to cache allocation
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Systems, apparatuses, and methods related to a block-based processor core topology register are disclosed. In one example of the disclosed technology, a processor can include a plurality of block-based processor cores for executing a program including a plurality of instruction blocks. A respective block-based processor core can include a sharable resource and a programmable composition topology register. The programmable composition topology register can be used to assign a group of the physical processor cores that share the sharable resource.

## Claims

### Claim 1

A processor comprising a plurality of physical processor cores for executing a program comprising a plurality of instruction blocks, the processor comprising:
a branch predictor configured to select a first group of instructions to be speculatively executed by a logical processor; and
a programmable composition topology register for assigning a number of physical processor cores of the plurality of physical processor cores to the logical processor, the programmable composition topology register being dynamically programmable during execution of the program, the composition topology register comprising a composition field and a mode field for specifying a meaning of the composition field, the composition field providing a bit-map of the physical processor cores of the logical processor when the mode field is programmed with a first value, and the composition field providing the number of the physical processor cores of the logical processor when the mode field is programmed with a second value.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the physical processor cores of the logical processor are determined by the number of the physical processor cores programmed in the composition topology register and a position of the respective physical processor core within a topology of the processor.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the physical processor cores of the logical processor are programmed using a composition field of the composition topology register that identifies each physical processor core of the logical processor.

### Claim 4 (depends on 1)

The processor of claim 1, further comprising:
one or more sharable resources configurable to be shared by the physical processor cores of the logical processor, the one or more sharable resources used for executing instructions executing on the logical processor; and
a programmable composition control register for configuring which of the one or more sharable resources are shared with other physical processor cores of the logical processor.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the composition topology register is programmable in part by performing a store instruction executing on any of the plurality of cores to a memory-mapped address corresponding to the composition topology register.

### Claim 6 (depends on 5)

The processor of claim 5, wherein a value of the composition topology register is updated during a commit phase of the store instruction to the memory-mapped address corresponding to the composition topology register.

### Claim 7

A processor comprising a plurality of physical processor cores for executing a plurality of instructions, a respective physical processor core comprising:
a sharable resource configurable to be shared with a group of physical processor cores of the plurality of physical processor cores, the sharable resource used for executing instructions on the group of physical processor cores; and
a programmable composition topology register for assigning the group of the physical processor cores that share the sharable resource, the programmable composition topology register being dynamically programmable during execution of the program, wherein the group of physical processor cores is programmed using a composition field of the composition topology register that identifies each physical processor core of the group of physical processor cores, and each physical processor core of the group of physical processor cores is identified with a bitmap of the physical processor cores.

### Claim 8 (depends on 7)

The processor of claim 7, wherein the respective physical processor core further comprises:
a programmable composition control register for selecting the sharable resource from one or more sharable resources of the respective processor core.

### Claim 9 (depends on 8)

The processor of claim 8, wherein the one or more sharable resources are selected from a data cache, a register file, or an execution unit.

### Claim 10 (depends on 7)

The processor of claim 7, wherein a value of a cache composition topology register is updated during a commit phase of a store instruction to a memory-mapped address corresponding to a cache topology control register.

### Claim 11

A method of executing a program on a processor comprising a first physical processor core and a second physical processor core, the program comprising a plurality of instructions arranged in one or more threads, the method comprising:
composing a logical processor comprising the first physical processor core and the second physical processor core according to a value stored in a composition topology register, the composition topology register comprising a composition field that identifies each physical processor core of a logical processor using a bitmap of the physical processor cores, the value stored in the composition topology register representing the bitmap of the physical processor cores;
non-speculatively executing a first set of instuctions of the thread on the first physical processor core; and
speculatively executing a second set of instructions of the thread on the second physical processor core.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
quiescing speculative execution for instructions executing after a plurality of thread initialization instructions;
performing a store operation to the composition topology register from within the plurality of thread initialization instruction blocks; and
performing a branch operation to the first set of instructions during a commit phase of the plurality of thread initialization instructions to initiate execution of the thread on the logical processor.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
during execution of the thread on the logical processor, selecting physical processor cores of the logical processor for speculatively executing instructions of the thread according to an allocation policy.

### Claim 14 (depends on 13)

The method of claim 13, wherein the allocation policy is round-robin scheduling of the physical processor cores of the logical processor.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
configuring sharing of a resource of the first physical processor core according to a composition control register of the first physical processor core.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
using the resource of the first physical processor core when executing an instruction of the second set of instructions on the second physical processor core.

### Claim 17 (depends on 11)

The method of claim 11, wherein the value stored in the composition topology register is generated by committing a store to an address mapped to the composition topology register of the processor.