# US 10,768,933 B2 · Streaming engine with stream metadata saving for context switching > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,768,933 B2 - Document ID: US10768933B2 - Status: Granted - Kind: B2 - Application number: 16/273,413 - Filed: 2019-02-12 - Published: 2019-06-06 - Granted: 2020-09-08 - Earliest claimed: 2013-07-15 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Joseph Zbiciak; Timothy D. Anderson - Web page: https://patentgrep.com/patent/US10768933B2 ## CPC - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30014: {with variable precision} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/3004: {to perform operations on memory} - G06F 9/30047: {Prefetch instructions; cache control instructions} - G06F 9/30098: {Register arrangements} - G06F 9/30112: {comprising data of variable length} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G06F 9/32: Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence) - G06F 9/34: Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} - G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)} - G06F 9/3802: {Instruction prefetching} - G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)} - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F 9/3867: {using instruction pipelines} - G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) - G06F 13/14: Handling requests for interconnection or transfer - G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's - G06F 2212/452: Instruction code - G06F 2212/60: Details of cache memory - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state. ## Claims ### Claim 1 A data processing apparatus comprising: a processing core; a memory; a register file; and a streaming engine configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, the streaming engine including: an address generator to generate addresses corresponding to locations in the memory; a buffer to store the plurality of data elements received from the locations in the memory corresponding to the generated addresses; and an output to supply the plurality of data elements received from the memory to the processing core as the data stream, wherein the streaming engine is: responsive to a stream save instruction to store state metadata of the data stream into at least one register of the register file; and responsive to a stream restore instruction to recall the state metadata of the data stream from the at least one register of the register file, wherein: the state metadata includes a current address, the current address being generated by the address generator and corresponding to a next data element to be fetched from the memory; the data stream includes a plurality of loops, each loop having a total iteration count representing a number of times the loop is to repeat; and the state metadata additionally includes information indicating remaining iterations for each of the loops. ### Claim 2 (depends on 1) The data processing apparatus of claim 1, wherein the total iteration count for each loop is specified by a stream definition template for the data stream. ### Claim 3 (depends on 2) The data processing apparatus of claim 2, wherein the streaming engine includes a stream template register to store the stream definition template. ### Claim 4 (depends on 1) The data processing apparatus of claim 1, wherein, after storing state meta data of the data stream into the at least one register of the register file in response to the stream save instruction, the streaming engine stops fetching the plurality of data elements of the data stream from the memory. ### Claim 5 (depends on 4) The data processing apparatus of claim 4, wherein, after recalling the state meta data of the data stream from the at least one register of the register in response to the stream restore instruction, the streaming engine resumes fetching the plurality of data elements of the data stream from the memory. ### Claim 6 (depends on 4) The data processing apparatus of claim 4, wherein, after storing state meta data of the data stream into the at least one register of the register file in response to the stream save instruction, the streaming engine discards a subset of the plurality of data elements of the data stream currently stored in the buffer. ### Claim 7 (depends on 4) The data processing apparatus of claim 4, wherein the stream save instruction is issued in response to a context switch event. ### Claim 8 (depends on 7) The data processing apparatus of claim 7, wherein the context switch event is an interrupt event. ### Claim 9 (depends on 2) The data processing apparatus of claim 2, wherein the state metadata additionally includes the stream definition template. ### Claim 10 (depends on 1) The data processing apparatus of claim 1, wherein the buffer is a first-in-first-out (FIFO) buffer. ### Claim 11 (depends on 1) The data processing apparatus of claim 1, wherein each data element of the data stream is of the same data element type. ### Claim 12 (depends on 1) The data processing apparatus of claim 1, further comprising a hierarchical memory system that includes a level one (L1) cache and a level two (L2) cache, wherein the memory is the L2 cache. ### Claim 13 (depends on 12) The data processing apparatus of claim 12, wherein the streaming engine is configured to provide for the transfer of the plurality of data elements of the data stream from the L2 cache to the processing core via a data path that does not includes the L1 cache. ### Claim 14 (depends on 1) The data processing apparatus of claim 1, wherein the processing core is a digital signal processing (DSP) core. ### Claim 15 (depends on 1) The data processing apparatus of claim 1, wherein the state metadata additionally includes a set of flags defining the data stream. ### Claim 16 (depends on 15) The data processing apparatus of claim 15, wherein the set of flags includes a flag that specifies an operation to be performed by the streaming engine from a group consisting of: promotion, duplication, and decimation. ### Claim 17 (depends on 1) The data processing apparatus of claim 1, wherein the state metadata additionally includes an address that corresponds to a next element to be fetched from the memory. ### Claim 18 A data processing apparatus comprising: a processing core; a memory; a register file; and a streaming engine configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, the streaming engine including: an address generator to generate addresses corresponding to locations in the memory, wherein the address generator includes an address register to store an address generated by the address generator which corresponds to a next element to be fetched from the memory; a buffer to store the plurality of data elements received from the locations in the memory corresponding to the generated addresses; and an output to supply the plurality of data elements received from the memory to the processing core as the data stream, wherein the streaming engine is: responsive to a stream save instruction to store state metadata of the data stream into at least one register of the register file; responsive to the stream save instruction to store the content of the address register into a first register of the at least one registers of the register file; responsive to a stream restore instruction to recall the state metadata of the data stream from the at least one register of the register file; and responsive to the stream restore instruction to store the content of the first register into the address register. ### Claim 19 (depends on 18) The data processing apparatus of claim 18 further comprising a level one (L1) cache, wherein: the memory is a level two (L2) cache; and the streaming engine includes an interface to the L2 cache via a data path that does not include the L1 cache. ### Claim 20 A data processing apparatus comprising: a processing core; a memory; a register file; and a streaming engine configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, the streaming engine including: an address generator to generate addresses corresponding to locations in the memory; a buffer to store the plurality of data elements received from the locations in the memory corresponding to the generated addresses; and an output to supply the plurality of data elements received from the memory to the processing core as the data stream, wherein the streaming engine is: responsive to a stream save instruction to store state metadata of the data stream into at least one register of the register file; and responsive to a stream restore instruction to recall the state metadata of the data stream from the at least one register of the register file, wherein: after storing state meta data of the data stream into the at least one register of the register file in response to the stream save instruction, the streaming engine stops fetching the plurality of data elements of the data stream from the memory; the stream save instruction is issued in response to a context switch event; the context switch event is an interrupt event; the streaming engine is configured to be, at any time, in one of an inactive state, an active state, and a frozen state; when an interrupt event occurs while the streaming engine is in the inactive state or in the frozen state, the streaming engine does not change its current state; when an interrupt event occurs while the streaming engine is in the active state, the streaming engine changes from the active state to the frozen state; when a return from an interrupt even occurs while the streaming engine is in the inactive state, the streaming engine does not change its current state; and when a return from an interrupt even occurs while the streaming engine is in the frozen state, the streaming engine changes from the frozen state to the active state.