# US 10,768,932 B2 · Information processing system, arithmetic processing circuit, and control method for information processing system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,768,932 B2 - Document ID: US10768932B2 - Status: Granted - Kind: B2 - Application number: 16/174,348 - Filed: 2018-10-30 - Published: 2019-05-09 - Granted: 2020-09-08 - Earliest claimed: 2017-11-06 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Akihiko Kasagi - Web page: https://patentgrep.com/patent/US10768932B2 ## CPC - G06F 9/3001: {Arithmetic instructions} - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - G06F 2213/0024: Peripheral component interconnect [PCI] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An arithmetic processing circuit includes, a dividing circuit that divides a plurality of data blocks into groups of a number equal to the number of arithmetic processing circuits included in an information processing apparatus, a data selecting circuit that selects respective first data blocks from the plurality of data blocks included in the respective groups, a transmission destination selecting circuit that selects arithmetic processing circuits different from each other as respective transmission destinations from the plurality of arithmetic processing circuits for the respective first data blocks selected by the data selecting circuit based on destination number information obtained by exclusive disjunction operation on identification number information assigned to each arithmetic processing circuit and cyclic number information assigned to each group, and a transmitting circuit that transmits the respective first data blocks selected by the data selecting circuit to the respective arithmetic processing circuits selected by the transmission destination selecting circuit. ## Claims ### Claim 1 An information processing system comprising a plurality of information processing apparatuses, each of the plurality of information processing apparatuses incorporating a plurality of arithmetic processing circuits, each of the plurality of arithmetic processing circuits includes: a dividing circuit configured to divide a plurality of data blocks retained by the arithmetic processing circuit into groups of a number equal to the number of the plurality of arithmetic processing circuits included in the information processing apparatus including the own device, a data selecting circuit configured to select respective first data blocks from the plurality of data blocks included in the respective groups, a transmission destination selecting circuit configured to select arithmetic processing circuits different from each other as respective transmission destinations from the plurality of arithmetic processing circuits included in the information processing apparatus for the respective first data blocks selected by the data selecting circuit based on destination number information obtained by exclusive disjunction operation on identification number information assigned to each arithmetic processing circuit and cyclic number information assigned to each group, and a transmitting circuit configured to transmit the respective first data blocks selected by the data selecting circuit to the respective arithmetic processing circuits selected by the transmission destination selecting circuit. ### Claim 2 (depends on 1) The information processing system according to claim 1, wherein the transmission destination selecting circuit selects, as the transmission destinations, the arithmetic processing circuits different from each other from arithmetic processing circuits adjacent to the own device among the plurality of arithmetic processing circuits included in the information processing apparatus. ### Claim 3 (depends on 2) The information processing system according to claim 2, wherein each of the arithmetic processing circuits is assigned the identification number information represented by a number of bits, the number of bits being the number of arithmetic processing circuits adjacent to the own device, and the transmission destination selecting circuit assigns the cyclic number information represented by the number of bits to each group, performs exclusive disjunction operation on the identification number information assigned to the own device and the cyclic number information, and selects an arithmetic processing circuit assigned identification number information coinciding with destination number information obtained by the exclusive disjunction operation as the transmission destination of the group assigned the cyclic number information used in the exclusive disjunction operation. ### Claim 4 (depends on 3) The information processing system according to claim 3, wherein the arithmetic processing circuit further includes a receiving circuit configured to receive a first data block transmitted from another arithmetic processing circuit, performs operation using a given data block corresponding to the received first data block among the plurality of data blocks and the received first data block, and set a result of the operation as data of the given data block. ### Claim 5 (depends on 4) The information processing system according to claim 4, wherein the transmission destination selecting circuit shifts the cyclic number information by one after the transmitting of the first data blocks by the transmitting circuit and storing of the result of the operation by the receiving circuit are completed. ### Claim 6 (depends on 5) The information processing system according to claim 5, wherein the data selecting circuit selects second data blocks from the respective groups after the transmitting of the first data blocks by the transmitting circuit and the storing of the result of the operation by the receiving circuit are completed, by performing exclusive disjunction operation on the identification number information and the cyclic number information shifted by one, the transmission destination selecting circuit selects arithmetic processing circuits different from each other for the respective second data blocks selected by the data selecting circuit and different from the transmission destinations of the first data blocks in the groups including the respective second data blocks as transmission destinations from among the plurality of arithmetic processing circuits included in the information processing apparatus, and the transmitting circuit transmits the respective second data blocks selected by the data selecting circuit to the arithmetic processing circuits selected by the transmission destination selecting circuit. ### Claim 7 (depends on 6) The information processing system according to claim 6, wherein the transmission destination selecting circuit selects, as the transmission destinations, arithmetic processing circuits retaining third data blocks as complementing counterparts of the second data blocks. ### Claim 8 (depends on 1) The information processing system according to claim 1, wherein the data blocks are a data group obtained by dividing data retained by the arithmetic processing circuit into a value obtained by multiplying a number resulting from raising two to a power of the number of adjacent arithmetic processing circuits by the number of the adjacent arithmetic processing circuits. ### Claim 9 (depends on 1) The information processing system according to claim 1, wherein the arithmetic processing circuits are each assigned the identification number information represented by given bits, and arithmetic processing circuits different from each other in a value of one bit in the identification number information are coupled to each other. ### Claim 10 An arithmetic processing circuit comprising: a dividing circuit configured to divide a plurality of data blocks retained by the arithmetic processing circuit into groups of a number equal to the number of arithmetic processing circuits included in an information processing apparatus incorporating the own arithmetic processing circuit; a data selecting circuit configured to select respective first data blocks from the plurality of data blocks included in the respective groups; a transmission destination selecting circuit configured to select arithmetic processing circuits different from each other as respective transmission destinations from the plurality of arithmetic processing circuits included in the information processing apparatus for the respective first data blocks selected by the data selecting circuit based on destination number information obtained by exclusive disjunction operation on identification number information assigned to each arithmetic processing circuit and cyclic number information assigned to each group; and a transmitting circuit configured to transmit the respective first data blocks selected by the data selecting circuit to the respective arithmetic processing circuits selected by the transmission destination selecting circuit. ### Claim 11 (depends on 10) The arithmetic processing circuit according to claim 10, wherein the transmission destination selecting circuit selects, as the transmission destinations, the arithmetic processing circuits different from each other from arithmetic processing circuits adjacent to the own device among the plurality of arithmetic processing circuits included in the information processing apparatus. ### Claim 12 (depends on 11) The arithmetic processing circuit according to claim 11, wherein each of the arithmetic processing circuits is assigned the identification number information represented by a number of bits, the number of bits being the number of arithmetic processing circuits adjacent to the own device, and the transmission destination selecting circuit assigns the cyclic number information represented by the number of bits to each group, performs exclusive disjunction operation on the identification number information assigned to the own device and the cyclic number information, and selects an arithmetic processing circuit assigned identification number information coinciding with destination number information obtained by the exclusive disjunction operation as the transmission destination of the group assigned the cyclic number information used in the exclusive disjunction operation. ### Claim 13 (depends on 12) The arithmetic processing circuit according to claim 12, wherein the arithmetic processing circuit further includes a receiving circuit configured to receive a first data block transmitted from another arithmetic processing circuit, performs operation using a given data block corresponding to the received first data block among the plurality of data blocks and the received first data block, and set a result of the operation as data of the given data block. ### Claim 14 (depends on 13) The arithmetic processing circuit according to claim 13, wherein the transmission destination selecting circuit shifts the cyclic number information by one after the transmitting of the first data blocks by the transmitting circuit and storing of the result of the operation by the receiving circuit are completed. ### Claim 15 (depends on 14) The arithmetic processing circuit according to claim 14, wherein the data selecting circuit selects second data blocks from the respective groups after the transmitting of the first data blocks by the transmitting circuit and the storing of the result of the operation by the receiving circuit are completed, by performing exclusive disjunction operation on the identification number information and the cyclic number information shifted by one, the transmission destination selecting circuit selects arithmetic processing circuits different from each other for the respective second data blocks selected by the data selecting circuit and different from the transmission destinations of the first data blocks in the groups including the respective second data blocks as transmission destinations from among the plurality of arithmetic processing circuits included in the information processing apparatus, and the transmitting circuit transmits the respective second data blocks selected by the data selecting circuit to the arithmetic processing circuits selected by the transmission destination selecting circuit. ### Claim 16 (depends on 15) The arithmetic processing circuit according to claim 15, wherein the transmission destination selecting circuit selects, as the transmission destinations, arithmetic processing circuits retaining third data blocks as complementing counterparts of the second data blocks. ### Claim 17 (depends on 10) The arithmetic processing circuit according to claim 10, wherein the data blocks are a data group obtained by dividing data retained by the arithmetic processing circuit into a value obtained by multiplying a number resulting from raising two to a power of the number of adjacent arithmetic processing circuits by the number of the adjacent arithmetic processing circuits. ### Claim 18 (depends on 10) The arithmetic processing circuit according to claim 10, wherein the arithmetic processing circuits are each assigned the identification number information represented by given bits, and arithmetic processing circuits different from each other in a value of one bit in the identification number information are coupled to each other. ### Claim 19 A control method for an information processing system including a plurality of information processing apparatuses, each of the plurality of information processing apparatuses incorporating a plurality of arithmetic processing circuits, each of the plurality of arithmetic processing circuits including a dividing circuit, a data selecting circuit, a transmission destination selecting circuit, and a transmitting circuit, the method comprising: dividing, by the dividing circuit, a plurality of data blocks retained by the arithmetic processing circuit into groups of a number equal to the number of the plurality of arithmetic processing circuits included in the information processing apparatus including the own device; selecting, by the data selecting circuit, respective first data blocks from the plurality of data blocks included in the respective groups; selecting, by the transmission destination selecting circuit, arithmetic processing circuits different from each other as respective transmission destinations from the plurality of arithmetic processing circuits included in the information processing apparatus for the respective first data blocks selected by the data selecting circuit based on destination number information obtained by exclusive disjunction operation on identification number information assigned to each arithmetic processing circuit and cyclic number information assigned to each group; and transmitting, by the transmitting circuit, the respective first data blocks selected by the data selecting circuit to the respective arithmetic processing circuits selected by the transmission destination selecting circuit.