# US 10,768,899 B2 · Matrix normal/transpose read and a reconfigurable data processor including same

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- Number: US 10,768,899 B2
- Document ID: US10768899B2
- Status: Granted
- Kind: B2
- Application number: 16/260,548
- Filed: 2019-01-29
- Published: 2020-07-30
- Granted: 2020-09-08
- Earliest claimed: 2019-01-29
- Assignees: SambaNova Systems, Inc.
- Applicants: SambaNova Systems, Inc.
- Inventors: David Alan Koeplinger; Raghu Prabhakar; Ram Sivaramakrishnan; David Brian Jackson; Mark Luttrell
- Web page: https://patentgrep.com/patent/US10768899B2

## CPC

- G06F 7/78: for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
- G06F 5/08: having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register {(G06F5/065 takes precedence; shift registers per se G11C19/00)}
- G06F 7/768: {Data position reversal, e.g. bit reversal, byte swapping}
- G06F 12/0207: {with multidimensional access, e.g. row/column, matrix}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G06F 2207/4824: Neural networks
- G11C 11/419: Read-write [R-W] circuits
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A configurable circuit configurable according to the data width of elements of a matrix is described that includes a memory array, logic to write a matrix to the memory array having elements with a data width which can be specified using configuration data, logic for a transpose read of the matrix as-written and logic for normal read of the matrix as-written. The memory array includes first and second read ports operable in parallel. Transpose read logic and normal read logic can be coupled to the first and second read ports, respectively, allowing transpose and normal read of a matrix simultaneously.

## Claims

### Claim 1

A configurable circuit, comprising:
a memory array;
logic to write a matrix to the memory array, the matrix having elements with a data width having a number D of bits of data;
transpose read logic configurable according to the data width, to output vectors of a transpose read of the matrix; and
normal read logic to output vectors of a normal read of the matrix;
wherein the transpose read logic and the normal read logic are operable on the memory array to output in parallel respective vectors in transposed and normal orders.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the memory array includes a first read port and a second read port, and the normal read logic is operably coupled to the first read port and the transpose read logic is operably coupled to the second read port.

### Claim 3

A configurable circuit, comprising:
a memory array;
logic to write a matrix to the memory array, the matrix having elements with a data width having a number D of bits of data;
transpose read logic configurable according to the data width, to output vectors of a transpose read of the matrix; and
normal read logic to output vectors of a normal read of the matrix;
wherein the memory array includes a plurality of slots, where slots in the plurality of slots include have a slot width (number of columns) equal to a multiple M greater than 1 of the data width.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the logic to write comprises logic to organize sets of M rows of the matrix in the memory into a plurality of rows of atoms of M by M elements, atoms in a row of atoms being stored in respective slots in the plurality of slots, and rotated in position in the row of atoms relative to an input matrix as a function of a row number of the row of atoms in the plurality of rows of atoms.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein the transpose read logic includes logic to select atoms in the slots, and store the selected atoms in a reshape circuit, and logic to transpose the selected atoms to form the output vectors of the transpose read of the matrix.

### Claim 6 (depends on 5)

The circuit of claim 5, wherein the reshape circuit includes a FIFO buffer having a depth at least as high as a maximum of M according to the data width of the elements of the matrix, and the logic to transpose the atoms includes a multiplexer tree configurable according to the data width.

### Claim 7 (depends on 5)

The circuit of claim 5, including logic to operate the reshape circuit using double buffering.

### Claim 8 (depends on 5)

The circuit of claim 5, wherein the transpose read logic is configurable for a selected one of a plurality of data types, and in which the data width differs for different data types in the plurality of data types.

### Claim 9 (depends on 3)

The circuit of claim 3, wherein the transpose read logic is configurable for a selected one of a plurality of data types, and the data widths differ for different data types in the plurality of data types, and the slot width is at least two times a maximum of the data width of data types in the plurality of data types.

### Claim 10

A reconfigurable data processor, comprising:
an array of configurable units; and
a bus system connected to the array of configurable units which communicates data at a bus clock rate; wherein a configurable unit in the array of configurable units includes:
a memory array,
logic to write a matrix to the memory array at the bus clock rate, the matrix having elements with a data width having a number D of bits of data; and
transpose read logic configurable according to the data width, to output vectors of a transpose read of the matrix at the bus clock rate,
wherein the transpose read logic and the normal read logic are operable on the memory array to output in parallel respective vectors in transposed and normal orders.

### Claim 11 (depends on 10)

The reconfigurable data processor of claim 10, including normal read logic configurable according to the data width, to output vectors of a normal read of the matrix at the bus clock rate, and wherein the memory array includes a first read port and a second read port, and the normal read port is operably coupled to the first read port, and the transpose read logic is operably coupled to the second read port.

### Claim 12

A reconfigurable data processor, comprising:
an array of configurable units; and
a bus system connected to the array of configurable units which communicates data at a bus clock rate; wherein a configurable unit in the array of configurable units includes:
a memory array,
logic to write a matrix to the memory array at the bus clock rate, the matrix having elements with a data width having a number D of bits of data; and
transpose read logic configurable according to the data width, to output vectors of a transpose read of the matrix at the bus clock rate;
wherein the memory array includes a plurality of slots, where slots in the plurality of slots include having a slot width (number of columns) equal to a multiple M greater than 1 of the data width.

### Claim 13 (depends on 12)

The reconfigurable data processor of claim 12, wherein the transpose read logic includes write logic to organize sets of M rows of the matrix in the memory into a plurality of rows of atoms of M by M elements, atoms in a row of atoms being stored in respective slots in the plurality of slots, and rotated in position in the row of atoms relative to an input matrix as a function of a row number of the row of atoms in the plurality of rows of atoms.

### Claim 14 (depends on 13)

The reconfigurable data processor of claim 13, wherein the transpose read logic includes logic to select atoms in the slots, and store the selected atoms in a reshape circuit, the reshape circuit including circuits to transpose the selected atoms to form the output vectors of the transpose read of the matrix.

### Claim 15 (depends on 14)

The reconfigurable data processor of claim 14, wherein the reshape circuit includes a FIFO buffer having a depth at least as high as a maximum of M according to the data type of the elements of the matrix, and the circuit to transpose the atoms comprises a multiplexer tree configurable according to the data width.

### Claim 16 (depends on 14)

The reconfigurable data processor of claim 14, including logic to operate the reshape circuit using double buffering.

### Claim 17 (depends on 14)

The reconfigurable data processor of claim 14, wherein the transpose read logic is configurable for a selected one of a plurality of data types, and in which the data width differs for different data types in the plurality of data types.

### Claim 18 (depends on 12)

The reconfigurable data processor of claim 12, wherein the transpose read logic is configurable for a selected one of a plurality of data types, and in which the data width differs for different data types in the plurality of data types, and the slot width is at least two times a maximum of the data width of data types in the plurality of data types.

### Claim 19

A memory circuit, comprising:
a memory array;
write logic to write a matrix to the memory array, the matrix having elements with a data width having a number D of bits of data, wherein the memory array includes a plurality of slots readable in parallel on different rows, where slots in the plurality of slots have a slot width equal to a multiple M of the data width, with logic to organize, when M is greater than 1, sets of M rows of the matrix in the memory array into a plurality of rows of atoms of M by M elements, so that atoms in a row of atoms are stored in respective slots in the plurality of slots, and rotated in position in the row of atoms relative to an input matrix as a function of a row number of the row of atoms in the plurality of rows of atoms; and
transpose read logic to output vectors of a transpose read of the matrix, including logic to select atoms in the slots, and store the selected atoms in a reshape circuit, the reshape circuit including circuits to transpose the selected atoms to form output vectors of a transpose read of the matrix.

### Claim 20 (depends on 19)

The circuit of claim 19, wherein the memory array includes a first read port and a second read port, and including normal read logic to output vectors of a normal read of the matrix operably coupled to the first read port, wherein the transpose read logic is operably coupled to the second read port.

### Claim 21 (depends on 20)

The circuit of claim 20, wherein the first read port and the second read port are operable in parallel.

### Claim 22 (depends on 19)

The circuit of claim 19, wherein the reshape circuit includes a FIFO buffer having a depth at least as high as a maximum of M according to the data width, and a multiplexer tree.

### Claim 23 (depends on 22)

The circuit of claim 22, including logic to operate the FIFO using double buffering.

### Claim 24 (depends on 19)

The circuit of claim 19, wherein the slot width is at least two times a maximum of the data width.

### Claim 25

A memory circuit for transpose read of a matrix, comprising:
memory;
means for organizing sets of M rows of a matrix into a plurality of slots having a slot width of M elements in the memory into a plurality of rows of atoms of M by M elements, atoms in a row of atoms being stored in respective slots in the memory, and rotated in position in the row of atoms relative to an input matrix as a function of a row number of the row of atoms in the plurality of rows of atoms; and
means for selecting atoms in the slots to be read, and transposing the selected atoms to form output vectors of the transpose read of the matrix.