# US 10,768,896 B2 · Apparatus and method for processing fractional reciprocal operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,768,896 B2 - Document ID: US10768896B2 - Status: Granted - Kind: B2 - Application number: 15/850,636 - Filed: 2017-12-21 - Published: 2019-06-27 - Granted: 2020-09-08 - Earliest claimed: 2017-12-21 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Cristina Anderson; Elmoustapha Ould-Ahmed-Vall; Marius Cornea-Hasegan; Robert Valentine; Mark Charney; Jesus Corbal; Venkateswara Madduri - Web page: https://patentgrep.com/patent/US10768896B2 ## CPC - G06F 7/5525: {Roots or inverse roots of single operands} - G06F 7/535: Dividing only - G06F 9/30014: {with variable precision} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/30101: {Special purpose registers} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 2207/5356: Via reciprocal, i.e. calculate reciprocal only, or calculate reciprocal first and then the quotient from the reciprocal and the numerator - G06F 2207/5521: Inverse root of a number or a function, e.g. the reciprocal of a Pythagorean sum - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method for performing a reciprocal. For example one embodiment of a processor comprises: a decoder to decode a reciprocal instruction to generate a decoded reciprocal instruction; a source register to store at least one packed input data element; a destination register to store a result data element; and reciprocal execution circuitry to execute the decoded reciprocal instruction, the reciprocal execution circuitry to use a first portion of the packed input data element as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets, the reciprocal execution circuitry to generate a reciprocal of the packed input data element using a combination of the coefficients and a second portion of the packed input data element. ## Claims ### Claim 1 A processor comprising: a decoder to decode an instruction; a source register to store at least one packed input data element; a destination register to store a result data element; and execution circuitry to execute the decoded instruction, the execution circuitry to use a first portion of the packed input data element as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets, wherein the packed input data element comprises a doubleword and wherein the first portion of the packed input data element comprises two bits to index a coefficient table containing four entries, and the execution circuitry to generate a reciprocal of the packed input data element using a combination of the coefficients and a second portion of the packed input data element and store the reciprocal in the destination register as the result data element, wherein combining the coefficients with the second portion of the packed input data element comprises multiplications of the coefficients and the second portion of the packed input data element. ### Claim 2 (depends on 1) The processor of claim 1 wherein the packed input data element comprises a word and wherein the first portion of the packed input data element comprises three bits to index a coefficient table containing eight entries. ### Claim 3 (depends on 1) The processor of claim 1 wherein combining the coefficients with the second portion of the packed input data element comprises evaluating a polynomial function with the coefficients as polynomial coefficients and the second portion of the packed input data element as input to the polynomial function. ### Claim 4 (depends on 3) The processor of claim 3 wherein the polynomial function comprises c3*R3+c2*R2+c1*R+c0 wherein c0, c1, c2, and c3 are the coefficients and R is the second portion of the packed input data element. ### Claim 5 (depends on 1) The processor of claim 1 wherein the execution circuitry comprises a plurality of multipliers to multiply one or more of the first set of coefficients by the second portion of the packed input data or data values derived from the second portion of the packed input data, the multiplications generating a plurality of temporary products. ### Claim 6 (depends on 5) The processor of claim 5 wherein the execution circuitry further comprises an adder network to add the temporary products to generate a result. ### Claim 7 (depends on 6) The processor of claim 6 further comprising: Newton-Raphson circuitry and/or logic to implement approximation techniques to improve accuracy of the result to generate a final result. ### Claim 8 (depends on 7) The processor of claim 7 wherein the final result is to be stored as a packed data element in the destination register. ### Claim 9 A method comprising: decoding an instruction; executing the decoded instruction to use a first portion of a packed input data element of a source register as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets, wherein the packed input data element comprises a doubleword and wherein the first portion of the packed input data element comprises two bits to index a coefficient table containing four entries, and generating and storing in a destination register a reciprocal of the packed input data element using a combination of the coefficients and a second portion of the packed input data element, wherein combining the coefficients with the second portion of the packed input data element comprises multiplications of the coefficients and the second portion of the packed input data element. ### Claim 10 (depends on 9) The method of claim 9 wherein the packed input data element comprises a word and wherein the first portion of the packed input data element comprises three bits to index a coefficient table containing eight entries. ### Claim 11 (depends on 9) The method of claim 9 wherein combining the coefficients with the second portion of the packed input data element comprises evaluating a polynomial function with the coefficients as polynomial coefficients and the second portion of the packed input data element as input to the polynomial function. ### Claim 12 (depends on 11) The method of claim 11 wherein the polynomial function comprises c3*R3+c2*R2+c1*R+c0 wherein c0, c1, c2, and c3 are the coefficients and R is the second portion of the packed input data element. ### Claim 13 (depends on 9) The method of claim 9 wherein a plurality of multipliers is to multiply one or more of the first set of coefficients by the second portion of the packed input data or data values derived from the second portion of the packed input data, the multiplications generating a plurality of temporary products. ### Claim 14 (depends on 13) The method of claim 13 wherein an adder network is to add the temporary products to generate a result. ### Claim 15 (depends on 14) The method of claim 14, further comprising: implementing approximation techniques to improve accuracy of the result to generate a final result. ### Claim 16 (depends on 15) The method of claim 15 wherein the final result is to be stored as a packed data element in the destination register. ### Claim 17 A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of: decoding an instruction; executing the decoded instruction to use a first portion of a packed input data element of a source register as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets, wherein the packed input data element comprises a word and wherein the first portion of the packed input data element comprises three bits to index a coefficient table containing eight entries, and generating and storing in a destination register a reciprocal of the packed input data element using a combination of the coefficients and a second portion of the packed input data element, wherein combining the coefficients with the second portion of the packed input data element comprises multiplications of the coefficients and the second portion of the packed input data element. ### Claim 18 (depends on 17) The non-transitory machine-readable medium of claim 17 wherein the packed input data element comprises a doubleword and wherein the first portion of the packed input data element comprises two bits to index a coefficient table containing four entries. ### Claim 19 (depends on 17) The non-transitory machine-readable medium of claim 17 wherein combining the coefficients with the second portion of the packed input data element comprises evaluating a polynomial function with the coefficients as polynomial coefficients and the second portion of the packed input data element as input to the polynomial function. ### Claim 20 (depends on 19) The non-transitory machine-readable medium of claim 19 wherein the polynomial function comprises c3*R3+c2*R2+c1*R+c0 wherein c0, c1, c2, and c3 are the coefficients and R is the second portion of the packed input data element. ### Claim 21 (depends on 17) The non-transitory machine-readable medium of claim 17 wherein a plurality of multipliers is to multiply one or more of the first set of coefficients by the second portion of the packed input data or data values derived from the second portion of the packed input data, the multiplications generating a plurality of temporary products. ### Claim 22 (depends on 21) The non-transitory machine-readable medium of claim 21 wherein an adder network is to add the temporary products to generate a result. ### Claim 23 (depends on 22) The non-transitory machine-readable medium of claim 22, wherein the operations further comprise: implementing approximation techniques to improve accuracy of the result to generate a final result. ### Claim 24 (depends on 23) The non-transitory machine-readable medium of claim 23 wherein the final result is to be stored as a packed data element in the destination register.