# US 10,768,839 B2 · Memory system and operating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,768,839 B2 - Document ID: US10768839B2 - Status: Granted - Kind: B2 - Application number: 16/233,661 - Filed: 2018-12-27 - Published: 2020-02-06 - Granted: 2020-09-08 - Earliest claimed: 2018-08-03 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Eu-Joon Byun - Web page: https://patentgrep.com/patent/US10768839B2 ## CPC - G06F 3/064: {Management of blocks} - G11C 11/5671: {using charge trapping in an insulator} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 7/109: {Control signal input circuits} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/10: Programming or data input circuits - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0614: {Improving the reliability of storage systems} - G06F 3/0629: {Configuration or reconfiguration of storage systems} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory system includes: a plurality of memory devices, each of which includes a first block and a second block; and a controller suitable for: storing data received from a host in a buffer; selecting a first block, of a memory device of the plurality of memory devices, to be programmed with the data; detecting a size of the data; controlling the memory device to program the data into the selected first block when the size is detected to be equal to a one-shot program size; determining a status of the memory device including the selected first block when the size is detected to be smaller than the one-shot program size; controlling the memory device to program the data into the selected first block when the memory device including the selected first block is determined to be in a first status; and controlling the memory device to program the data into the second block of the memory device when it is determined to be is a second status. ## Claims ### Claim 1 A memory system, comprising: a plurality of memory devices, each of which includes a first block and a second block; and a controller suitable for: storing data received from a host in a buffer; selecting the first block, of a memory device of the plurality of memory devices, to be programmed with the data; detecting a size of the data; controlling the memory device to program the data into the selected first block when the size is detected to be equal to a one-shot program size; determining a status of the memory device including the selected first block when the size is detected to be smaller than the one-shot program size; controlling the memory device to program the data into the selected first block when the status of the memory device including the selected first block is determined to be in an idle status; and controlling the memory device to program the data into the second block of the memory device when the status of the memory device including the selected first block is determined to be in a busy status, wherein the first block has a greater storage capacity than the second block, and the second block accommodates a faster storage speed than that of the first block. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the first block includes one among a multi-level cell (MLC), a triple level cell (TLC) and a quadruple level cell (QLC), and the second block includes a single level cell (SLC). ### Claim 3 (depends on 1) The memory system of claim 1, wherein the one-shot program size represents a size of data with which to perform a one-shot program operation onto the first block. ### Claim 4 (depends on 1) The memory system of claim 1, wherein, when the size is equal to the one-shot program size, the controller performs a one-shot program operation onto the selected first block without generating dummy data. ### Claim 5 (depends on 1) The memory system of claim 1, wherein, when the memory device including the selected first block is in the idle status, the controller generates dummy data and programs the data and the dummy data into the selected first block. ### Claim 6 (depends on 1) The memory system of claim 1, wherein: when the memory device including the selected first block is in the busy status, the controller changes the selected first block to the second block in the memory device including the selected first block, and when the memory device including the selected first block is in the idle status, the controller controls the memory device to program the data into the selected second block without dummy data. ### Claim 7 A method for operating a memory system including a plurality of memory devices, each of which includes a first block and a second block, and a controller suitable for controlling the memory devices, the method comprising: storing data received from a host in a buffer; selecting a first block of a memory device of the plurality of memory devices, to be programmed with the data; detecting a size of the data; controlling the memory device including the selected first block to program the data into the selected first block when the size is detected to be equal to a one-shot program size; determining a status of the memory device including the selected first block when the size is detected to be smaller than the one-shot program size; controlling the memory device to program the data into the selected first block when the memory device including the selected first block is in an idle status; and controlling the memory device to program the data into the second block when the memory device including the selected first block is in a busy status, wherein the first block has a greater storage capacity than the second block, and the second block accommodates a faster storage speed than that of the first block. ### Claim 8 (depends on 7) The method of claim 7, wherein in controlling the memory device including the selected first block to program the data into the selected first block when the size is detected to be equal to a one-shot program size, a one-shot program operation is performed onto the first block without generating dummy data. ### Claim 9 (depends on 7) The method of claim 7, wherein the first block includes one among a multi-level cell (MLC), a triple level cell (TLC) and a quadruple level cell (QLC), and the second block includes a single level cell (SLC). ### Claim 10 (depends on 7) The method of claim 7, wherein the one-shot program size represents a size of data with which to perform a one-shot program operation onto the first block. ### Claim 11 (depends on 7) The method of claim 7, wherein in determining the status of the memory device including the first block, it is determined whether the memory device is in an idle status or not. ### Claim 12 (depends on 7) The method of claim 7, wherein the controlling of the memory device including the selected first block to program the data into the selected first block when the memory device including the selected first block is in the idle status includes: generating dummy data; and programming the data and the dummy data into the selected first block. ### Claim 13 (depends on 7) The method of claim 7, wherein the controlling of the memory device including the selected first block to program the data into the second block when the memory device including the selected first block is in the busy status includes: changing the selected first block to the second block in the memory device including the selected first block; and controlling the memory device including the selected second block to program the data into the selected second block without dummy data. ### Claim 14 A memory system comprising: a memory device including first cells and second cells; and a controller suitable for: controlling the memory device to perform a one-shot program operation of storing target data into the first cells when a size of the target data is compatible with the one-shot program operation; controlling the memory device to perform the one-shot program operation of storing the target data and dummy data into the first cells when the size of the target data is not compatible with the one-shot program operation and the memory device is idle; and controlling the memory device to perform a normal program operation of storing the target data into the second cells when the size of the target data is not compatible with the one-shot program operation and the memory device is busy, wherein each of the first cells has a greater storage capacity than each of the second cells, and each of the second cells accommodates a faster storage speed than that of each of the first cells. ### Claim 15 A memory system, comprising: a plurality of memory devices, each of which include a plurality of blocks included a first block and a second block; and a controller suitable for: storing data received from a host in a buffer; selecting the first block, of a memory device of the plurality of memory devices, to be programmed with the data; detecting a size of the data; controlling the memory device to program the data into the selected first block when the size is detected to be equal to a one-shot program size; determining a status of the memory device including the selected first block when the size is detected to be smaller than the one-shot program size; controlling the memory device to program the data into the selected first block when the status of the memory device including the selected first block is determined to be in an idle status; and controlling the memory device to program the data into the second block of the memory device when the status of the memory device including the selected first block is determined to be in a busy status, wherein the controller classifies and controls the plurality of memory blocks included in each of the plurality of memory devices into the first block and the second block according to storage capacity and storage speed, and wherein the first block has a greater storage capacity than the second block, and the second block accommodates a faster storage speed than that of the first block. ### Claim 16 (depends on 15) The memory system of claim 15, wherein, when the memory device including the selected first block is in the idle status, the controller generates dummy data and programs the data and the dummy data into the selected first block. ### Claim 17 (depends on 15) The memory system of claim 15, wherein: when the memory device including the selected first block is in the busy status, the controller changes the selected first block to the second block in the memory device including the selected first block; and when the memory device including the selected first block is in the idle status, the controller controls the memory device to program the data into the selected second block without dummy data.