# US 10,768,828 B2 · Data movement between volatile and non-volatile memory in a read cache memory

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- Number: US 10,768,828 B2
- Document ID: US10768828B2
- Status: Granted
- Kind: B2
- Application number: 15/619,966
- Filed: 2017-06-12
- Published: 2017-09-28
- Granted: 2020-09-08
- Earliest claimed: 2014-05-20
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Eugene Feng; Mathew Arcoleo
- Web page: https://patentgrep.com/patent/US10768828B2

## CPC

- G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}
- G06F 3/0608: {Saving storage space on storage systems}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA]
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/765: {in solid state disks}
- G06F 2212/2532: comprising a plurality of modules
- G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
- G11C 2029/0409: {Online test}
- G11C 2207/2245: Memory devices with an internal cache buffer
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.

## Claims

### Claim 1

A method for operating a memory, comprising:
receiving a first set of cached data at a dynamic random-access memory (DRAM) array;
promoting a portion of the first set of cached data to a class of the DRAM array based on a data characteristic of the portion of the first set of cached data;
promoting a second set of cached data that is in a particular percentage range of most frequently accessed cached data of the cached data that has been accessed more than once from the class of the DRAM array to a first NAND array;
promoting a third set of cached data to a second NAND array in response to the first NAND array reaching a threshold capacity;
demoting the cached data of the third set of cached data to the DRAM array in response to the second NAND array reaching a different threshold capacity;
evicting a fourth set of cached data in the DRAM array in response to the DRAM array receiving a fifth set of cached data, wherein the fourth set of cached data does not meet a threshold requirement to be promoted to the class of the DRAM array, the first NAND array, or the second NAND array, and wherein the threshold requirement includes an access threshold; and
demoting a sixth set of cached data from the first NAND array to the DRAM in response to the sixth set of cached data failing to reach the threshold requirement.

### Claim 2 (depends on 1)

The method of claim 1, wherein the threshold requirement includes at least one of a request threshold and a stability threshold.

### Claim 3 (depends on 1)

The method of claim 1, further comprising swapping the first NAND array and the second NAND array such that the first NAND array becomes a new second NAND array and the second NAND array becomes a new first NAND array and repairing the first NAND array in response to the swapping.

### Claim 4 (depends on 1)

The method of claim 1, further comprising dynamically marking bad pages within the first NAND array.

### Claim 5 (depends on 1)

The method of claim 1, further comprising packing the portion of the first set of cached data in the class into packets sized to match page sizes within the first and the second NAND arrays.

### Claim 6 (depends on 1)

The method of claim 1, further comprising erasing the first NAND array in response to promoting the third set of cached data to the second NAND array.

### Claim 7

A method for operating a memory, comprising:
receiving cached data that is in a particular percentage range of most frequently accessed cached data that has been accessed more than once from a DRAM device to a primary NAND device;
evicting data from the primary NAND device that does not meet a threshold requirement to be promoted to a secondary NAND device in response to receiving the cached data from the DRAM device, wherein the threshold requirement includes an access threshold;
dynamically marking bad pages within the received cached data;
promoting a portion of the received cached data from the primary NAND to the secondary NAND in response to the primary NAND device reaching a threshold cached data capacity, and demoting the received cached data to the DRAM device in response to the secondary NAND reaching a different threshold capacity,
wherein the portion of the received cached data from the primary NAND device does not include the marked bad pages;
erasing the primary NAND array; and
swapping the primary and the secondary NAND devices such that the primary NAND device becomes a new secondary NAND device and the secondary NAND device becomes a new primary NAND device.

### Claim 8 (depends on 7)

The method of claim 7, wherein the cached data is received at the primary NAND device from the DRAM device via direct memory access (DMA).

### Claim 9 (depends on 7)

The method of claim 7, wherein the threshold requirement includes the portion of the received cached data being accessed a threshold number of times within a given time period.

### Claim 10 (depends on 7)

The method of claim 7, wherein the threshold requirement includes the portion of the received cached data meeting a threshold stability.

### Claim 11 (depends on 7)

The method of claim 7, wherein the method is performed iteratively.

### Claim 12 (depends on 7)

The method of claim 7, wherein receiving cached data comprises receiving a preset number of most-frequently visited page partitions from the DRAM device at the primary NAND device.

### Claim 13

An apparatus, comprising:
a memory device, comprising:
a dynamic random-access memory (DRAM); and
a first NAND array and a second NAND array; and
a controller configured to:
receive a first set of cached data at the DRAM array;
evict a second set of cached data from the DRAM array that does not meet a threshold requirement to be promoted to a class of the DRAM array, a first NAND array, or a second NAND array in response to receiving the first set of cached data, wherein the threshold requirement includes an access threshold;
promote a portion of the first set of cached data to the class of the DRAM array based on a data characteristic of the portion of the first set of cached data;
promote a third set of cached data that is in a particular percentage range of most frequently accessed cached data that has been accessed more than once from the class of the DRAM array to the first NAND array;
promote a fourth set of cached data to the second NAND array in response to the first NAND array reaching a threshold capacity;
demote the cached data of the fourth set of cached data to the DRAM array in response to the second NAND array reaching a different threshold capacity; and
demote a fifth set of cached data from the first NAND array to the DRAM in response to the fifth set of cached data failing to reach the threshold requirement.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the data characteristic includes a number of times the portion of the first set of cached data is requested.

### Claim 15 (depends on 13)

The apparatus of claim 13, wherein the data characteristic includes a stability of the portion of the first set of cached data.

### Claim 16 (depends on 13)

The apparatus of claim 13, wherein the different threshold capacity is based on a total amount of cached data within the second NAND array meeting a maximum threshold amount.

### Claim 17 (depends on 13)

The apparatus of claim 13, including the controller configured to store information associated with the portion of the first set of cached data and the fourth set of cached data.