# US 10,768,821 B2 · Memory system and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,768,821 B2 - Document ID: US10768821B2 - Status: Granted - Kind: B2 - Application number: 15/944,929 - Filed: 2018-04-04 - Published: 2019-02-14 - Granted: 2020-09-08 - Earliest claimed: 2017-08-08 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Sung Kwan Hong - Web page: https://patentgrep.com/patent/US10768821B2 ## CPC - G06F 3/0608: {Saving storage space on storage systems} - G06F 3/064: {Management of blocks} - G06F 3/0652: {Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket} - G06F 3/0658: {Controller construction arrangements} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0253: {Garbage collection, i.e. reclamation of unreferenced memory} - G06F 2212/1016: Performance improvement - G06F 2212/1044: Space efficiency improvement - G06F 2212/2022: Flash memory - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7205: Cleaning, compaction, garbage collection, erase control - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract There are provided a memory system for processing data and a method for operating the memory system. A memory system includes: a memory device including a plurality of memory blocks for storing data; and a controller for creating a SPOT table including a plurality of SPOT entries according to a logical block address (LBA) of the data and managing the SPOT table, using a least recently used (LRU) algorithm. ## Claims ### Claim 1 A memory system comprising: a memory device including a plurality of memory blocks for storing data; and a controller configured to include an assembly group table including a plurality of assembly group entries, and to include assembly group counts which correspond to the plurality of assembly group entries, respectively; wherein each of the plurality of assembly group entries includes a group of logical block addresses, wherein each of the assembly group counts represents a count of requests from a host for a corresponding assembly group entry, wherein the controller adds a new assembly group entry to the assembly group table according to a request from the host, wherein an assembly group count corresponding to the new assembly group entry is greater than each of the assembly group counts corresponding to each of the plurality of assembly group entries, wherein the controller performs a read reclaim operation on data corresponding to an assembly group entry of which an assembly group count exceeds a critical value, and wherein the controller registers an assembly group entry having an assembly group count larger than the critical value as a real assembly group by scanning the assembly group counts of the plurality of assembly group entries. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the controller includes: a memory configured to store the assembly group table; and a processor configured to manage the assembly group table stored in the memory. ### Claim 3 (depends on 2) The memory system of claim 2, wherein the plurality of assembly group entries correspond to different assembly group counts, respectively. ### Claim 4 (depends on 3) The memory system of claim 3, wherein the assembly group table is configured with the plurality of assembly group entries including a head entry and a tail entry, wherein the head entry represents an assembly group entry corresponding to a highest assembly group count among the plurality of assembly group entries, and wherein the tail entry represents an assembly group entry corresponding to a lowest assembly group count among the plurality of assembly group entries. ### Claim 5 (depends on 4) The memory system of claim 4, wherein, when the new assembly group entry is added to the assembly group table, the processor manages the assembly group table by designating the new assembly group entry as the head entry and moving the plurality of assembly group entries one by one in the direction of the tail entry. ### Claim 6 (depends on 5) The memory system of claim 5, wherein, when the new assembly group entry is added to the assembly group table, the processor deletes the tail entry. ### Claim 7 (depends on 4) The memory system of claim 4, wherein, when a read operation of a selected assembly group entry among the plurality of assembly group entries is performed in response to the request from the host, the processor moves the selected assembly group entry in the direction of the head entry by allowing an assembly group count of the selected assembly group entry to be increased by 1. ### Claim 8 (depends on 1) The memory system of claim 1, wherein, when the real assembly group is detected, the controller controls the memory device to perform the read reclaim operation on data corresponding to the real assembly group. ### Claim 9 A method for operating a memory system, the method comprising: creating an assembly group table including a plurality of assembly group entries each of which includes a group of logical block addresses requested from a host; allocating assembly group counts to the plurality of assembly group entries, respectively, wherein each of the assembly group counts represents a count of requests from the host for a corresponding entry; when a new assembly group entry is added to the assembly group table according to a request from the host, allocating an assembly group count greater than each of the assembly group counts corresponding to each of the plurality of assembly group entries, to the new assembly group entry, performing a read reclaim operation on data corresponding to an assembly group entry of which an assembly group count exceeds a critical value, and registering an assembly group entry having an assembly group count larger than the critical value as a real assembly group by scanning the assembly group counts of the plurality of assembly group entries. ### Claim 10 (depends on 9) The method of claim 9, wherein the plurality of assembly group entries have different assembly group counts, respectively. ### Claim 11 (depends on 10) The method of claim 10, further comprising, evicting a tail entry having a lowest assembly group count among the plurality of assembly group entries from the assembly group table when the new assembly group entry is added to the assembly group table. ### Claim 12 (depends on 10) The method of claim 10, wherein the read reclaim operation is performed on data having logical block addresses corresponding to the real assembly group. ### Claim 13 A memory controller comprising: a memory configured to store an assembly group table including a plurality of assembly group entries, and to store assembly group counts which correspond to the plurality of assembly group entries, respectively, wherein each of the plurality of assembly group entries includes a group of logical block addresses, wherein each of the assembly group counts represents a count of requests from a host for a corresponding assembly group entry; and a processor configured to control the memory to add a new assembly group entry to the assembly group table according to a request from the host, wherein an assembly group count corresponding to the new assembly group entry is greater than each of the assembly group counts corresponding to each of the plurality of assembly group entries, and wherein the processor performs a read reclaim operation on data corresponding to an assembly group entry of which an assembly group count exceeds a critical value, and registers an assembly group entry having an assembly group count larger than the critical value as a real assembly group by scanning the assembly group counts of the plurality of assembly group entries. ### Claim 14 (depends on 13) The memory controller of claim 13, wherein the plurality of assembly group entries correspond to different assembly group counts, respectively. ### Claim 15 (depends on 14) The memory controller of claim 14, wherein, when the processor adds the new assembly group entry to the assembly group table, the processor controls the memory to evict an assembly group entry corresponding to a lowest assembly group count, among the plurality of assembly group entries. ### Claim 16 (depends on 14) The memory controller of claim 14, wherein, when a request for a selected assembly group entry among the plurality of assembly group entries is transferred from the host to the memory controller, the processor controls the memory to move a location of the selected assembly group entry in a direction of a head entry on the assembly group table by increasing an assembly group count corresponding to the selected assembly group entry by 1, and wherein the head entry represents an assembly group entry corresponding to a highest assembly group count among the plurality of assembly group entries.