# US 10,768,688 B2 · Arithmetic processing device, information processing apparatus, and method for controlling arithmetic processing device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,768,688 B2 - Document ID: US10768688B2 - Status: Granted - Kind: B2 - Application number: 15/950,277 - Filed: 2018-04-11 - Published: 2018-10-25 - Granted: 2020-09-08 - Earliest claimed: 2017-04-19 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Megumi Ukai - Web page: https://patentgrep.com/patent/US10768688B2 ## CPC - G06F 1/3296: by lowering the supply or operating voltage - G06F 1/3228: Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands - G06F 13/00: Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor G06F9/46}; multiprocessor systems G06F15/16 ) - G06F 9/3001: {Arithmetic instructions} - H04L 67/10: in which an application is distributed across nodes in the network (software deployment G06F8/60; multiprogramming arrangements G06F9/46) - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract An arithmetic processing device includes: a communication interface configured to transmit a data request corresponding to a data request instruction stored in a data request queue that stores the data request instruction as an entry and to receive data corresponding to the transmitted data request; and a processor configured to perform an operation by using the data received by the communication interface, the processor is configured to cause the communication interface to transition to a power-saving state when the data request queue includes no entry and the processor performs the operation. ## Claims ### Claim 1 An arithmetic processing device comprising: a communication interface configured to transmit a data request corresponding to a data request instruction stored in a data request queue that stores the data request instruction as an entry and to receive data corresponding to the transmitted data request and an operation instruction; and a processor including a plurality of computing cores configured to perform an operation by using the data received by the communication interface, the processor is configured to: determine whether there is no entry in the data request queue; determine, when determining that there is no entry in the data request queue, whether one or more computing cores, which is to execute the operation instruction, are during execution by refereeing to a plurality of memories which are provided for the respective computing cores and store information indicating whether the respective computing cores are during execution; and cause the communication interface to transition to a power-saving state when at least one of the one or more computing cores are during execution. ### Claim 2 (depends on 1) The arithmetic processing device according to claim 1, wherein the processor is configured to start performing the operation in accordance with the operation instruction stored in an operation instruction queue which stores one or more operation instructions as one or more entries, respectively. ### Claim 3 (depends on 2) The arithmetic processing device according to claim 2, wherein the processor is configured to cause the communication interface to transition to the power-saving state when there is no entry in the data request queue, the at least one of the one or more computing cores are during execution and all of the one or more entries in the operation instruction queue are in use. ### Claim 4 (depends on 3) The arithmetic processing device according to claim 3, wherein the processor is configured to: if a condition register configured to store a first value or a second value stores the first value, cause the communication interface to transition to the power-saving state when there is no entry in the data request queue and the at least one of the one or more computing cores are during execution, and if the condition register stores the second value, cause the communication interface to transition to the power-saving state when there is no entry in the data request queue, the at least one of the one or more computing cores are during execution and all of the one or more entries in the operation instruction queue are in use. ### Claim 5 (depends on 1) The arithmetic processing device according to claim 1, wherein the processor is configured to cause the communication interface to transition, from the power-saving state, to a normal state when completing the operation. ### Claim 6 (depends on 5) The arithmetic processing device according to claim 5, wherein the processor is configured to cause the communication interface to transition, from the power-saving state via a recovery state, to the normal state when completing the operation. ### Claim 7 (depends on 1) The arithmetic processing device according to claim 1, wherein the processor is configured to: perform each of one or more operations in response to one operation instruction, and cause the communication interface to transition to the power-saving state when the data request queue includes no entry and the processor performs the one or more operations based on the one operation instruction. ### Claim 8 (depends on 5) The arithmetic processing device according to claim 5, wherein the processor is configured to: perform each of one or more operations in response to one operation instruction, and cause the communication interface to transition from the power-saving state to the normal state when completing an execution of all of the one or more operations based on the one operation instruction. ### Claim 9 (depends on 1) The arithmetic processing device according to claim 1, wherein the processor is configured to, when the communication interface receives the data corresponding to the transmitted data request, delete the data request instruction corresponding to the received data from the data request queue. ### Claim 10 (depends on 9) The arithmetic processing device according to claim 9, wherein the processor is configured to, when the communication interface receives a data request instruction, store the received data request instruction as an entry in the data request queue. ### Claim 11 (depends on 5) The arithmetic processing device according to claim 5, wherein the communication interface is configured to transmit an operation completion notification to outside after the operation is completed and the communication interface transitions to the normal state. ### Claim 12 (depends on 1) The arithmetic processing device according to claim 1, wherein the processor is configured to cause a physical layer of the communication interface to transition to the power-saving state. ### Claim 13 (depends on 1) The arithmetic processing device according to claim 1, wherein the communication interface is configured to, when the processor causes the communication interface to transition to the power-saving state, transmit a negotiation instruction to negotiate transition to the power-saving state and transition to the power-saving state when receiving a negotiation response corresponding to the negotiation instruction. ### Claim 14 (depends on 1) The arithmetic processing device according to claim 1, wherein the communication interface is configured to, when the processor causes the communication interface to transition to the power-saving state, transmit a negotiation instruction to negotiate transition to the power-saving state and causes a physical layer of the communication interface to the power-saving state when receiving a negotiation response corresponding to the transmitted negotiation instruction. ### Claim 15 (depends on 5) The arithmetic processing device according to claim 5, wherein the communication interface is configured to, when the processor causes the communication interface to transition to the normal state, transition from the power-saving state to a recovery state, transmit and receive an ordered set used for training, and transition from the recovery state to the normal state after the transmitting and receiving of the ordered set used for training. ### Claim 16 (depends on 5) The arithmetic processing device according to claim 5, wherein the communication interface is configured to, when the processor causes the communication interface to transition to the normal state, cause a physical layer of the communication interface to transition from the power-saving state to a recovery state, transmit and receive an ordered set for training, and cause the physical layer of the communication interface to transition from the recovery state to the normal state after transmitting and receiving the ordered set for training. ### Claim 17 An information processing apparatus comprising: an arithmetic processing device; and a host processing device coupled to the arithmetic processing device, the arithmetic processing device includes; a communication interface configured to transmit a data request corresponding to a data request instruction stored in a data request queue that stores the data request instruction as an entry and to receive data corresponding to the transmitted data request and an operation instruction; and a processor including a plurality of computing cores configured to perform an operation by using the data received by the communication interface, the processor is configured to: determine whether there is no entry in the data request queue; determine, when determining that there is no entry in the data request queue, whether one or more computing cores, which is to execute the operation instruction, are during execution by refereeing to a plurality of memories which are provided for the respective computing cores and store information indicating whether the respective computing cores are during execution; and cause the communication interface to transition to a power-saving state when at least one of the one or more computing cores are during execution. ### Claim 18 A method of controlling an arithmetic processing device comprising: transmitting, by a communication interface provided in the arithmetic processing device, a data request corresponding to a data request instruction stored in a data request queue that stores the data request instruction as an entry; receiving data corresponding to the transmitted data request and an operation instruction; performing, by a processor including a plurality of computing cores and provided in the arithmetic processing device, an operation by using the data received by the communication interface; determining whether there is no entry in the data request queue; determining, when determining that there is no entry in the data request queue, whether one or more computing cores, which is to execute the operation instruction, are during execution by refereeing to a plurality of memories which are provided for the respective computing cores and store information indicating whether the respective computing cores are during execution; and causing, by the processor, the communication interface to transition to a power-saving state when at least one of the one or more computing cores are during execution.