Memory system and controller
AssigneeToshiba Memory Corporation
InventorsYoshihisa Kojima, Katsuhiko Ueki
Life of this patent
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Abstract
In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.
Claims20
A memory system comprising:
- a nonvolatile memory;
- a controller circuit configured to receive a write command from a host and control the nonvolatile memory;
- and
- a battery configured to store power on the basis of power supplied from an external supply, wherein,
- if a completion response for a first write command has not been returned to the host in a case where power becomes unsupplied from the external supply, the controller circuit, using the power stored in the battery, aborts the first write command received from the host.
A method of controlling a memory system, the memory system including:
- a nonvolatile memory;
- a controller circuit;
- and
- a battery configured to store power on the basis of power supplied from an external supply,
- the method executed using the controller circuit, comprising:
- if a completion response for a first write command has not been returned to a host in a case where power becomes unsupplied from the external supply, aborting, using the power stored in the battery, the first write command received from the host.
Dependencies are inferred from the claim text.