# US 10,768,580 B2 · Time-to-digital converter, digital phase-locked loop, method for operating a time-to-digital converter, and method for a digital phase-locked loop > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,768,580 B2 - Document ID: US10768580B2 - Status: Granted - Kind: B2 - Application number: 16/474,562 - Filed: 2017-03-02 - Published: 2019-12-19 - Granted: 2020-09-08 - Earliest claimed: 2017-03-02 - Assignees: Intel IP Corporation - Applicants: Intel IP Corporation - Inventors: Yair Dgani; Michael Kerner; Elan Banin; Evgeny Shumaker; Gil Horovitz; Ofir Degani; Rotem Banin; Aryeh Farber; Rotem Avivi; Eshel Gordon; Tami Sela - Web page: https://patentgrep.com/patent/US10768580B2 ## CPC - G04F 10/005: {Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60)} - H03L 7/081: provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} - H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) - H03L 2207/50: All digital phase-locked loop - G04F: TIME-INTERVAL MEASURING (measuring pulse characteristics G01R, e.g. G01R29/02; in radar or like systems G01S) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal. ## Claims ### Claim 1 A time-to-digital converter, comprising: a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals; a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals; and a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal. ### Claim 2 (depends on 1) The time-to-digital converter of claim 1, wherein the predicted value of the phase of the oscillation signal is based on an output value of the time-to-digital converter, and wherein the output value of the time-to-digital converter indicates a phase difference between the reference signal and the oscillation signal. ### Claim 3 (depends on 2) The time-to-digital converter of claim 2, wherein the predicted value of the phase of the oscillation signal indicates a predicted phase of the oscillation signal in a second oscillation cycle of the oscillation signal that succeeds a first oscillation cycle of the oscillation signal for which the phase difference to the reference signal is determined by the time-to-digital converter. ### Claim 4 (depends on 1) The time-to-digital converter of claim 1, wherein at least one of the plurality of sample circuits comprises a plurality of flip-flop circuits. ### Claim 5 (depends on 4) The time-to-digital converter of claim 4, wherein a first portion of the plurality of flip-flop circuits is permanently activated, and wherein the control circuit is further configured to de-activate a second portion of the plurality of flip-flop circuits based on the predicted value of the phase of the oscillation signal. ### Claim 6 (depends on 1) The time-to-digital converter of claim 1, wherein the time-to-digital converter further comprises at least one switch circuit coupled between an input node of one of the plurality of sample circuits and a node of the time-to-digital converter that is configured to supply the oscillation signal to the one of the plurality of sample circuits, and wherein the control circuit is further configured to control the switch circuit to block a propagation of the oscillation signal to the one of the plurality of sample circuits based on the predicted value of the phase of the oscillation signal. ### Claim 7 (depends on 1) A digital phase-locked loop, comprising: a time-to-digital converter according to claim 1, wherein the time-to-digital converter is further configured to generate an output value indicative of a phase difference between the reference signal and the oscillation signal, and wherein the oscillation signal is generated by a controlled oscillator within the digital phase-locked loop; a decoder circuit configured to calculate, based on the output value of the time-to-digital converter, a current value of the phase of the oscillation signal; and a processing circuit configured to calculate, based on the current value of the phase of the oscillation signal, the predicted value of the phase of the oscillation signal. ### Claim 8 (depends on 7) The digital phase-locked loop of claim 7, wherein the processing circuit is further configured to calculate the predicted value of the phase of the oscillation signal based on a frequency of the oscillation signal. ### Claim 9 A method for operating a time-to-digital converter that comprises a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals, and a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals, wherein the method comprises: de-activating at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal. ### Claim 10 (depends on 9) The method of claim 9, wherein the predicted value of the phase of the oscillation signal is based on an output value of the time-to-digital converter, and wherein the output value of the time-to-digital converter indicates a phase difference between the reference signal and the oscillation signal. ### Claim 11 (depends on 10) The method of claim 10, wherein the predicted value of the phase of the oscillation signal indicates a predicted phase of the oscillation signal in a second oscillation cycle of the oscillation signal that succeeds a first oscillation cycle of the oscillation signal for which the phase difference to the reference signal is determined by the time-to-digital converter. ### Claim 12 (depends on 9) The method of claim 9, wherein at least the one of the plurality of sample circuits comprises a plurality of flip-flop circuits, wherein a first portion of the plurality of flip-flop circuits is permanently activated, and wherein de-activating at least one of the plurality of sample circuits comprises: de-activating a second portion of the plurality of flip-flop circuits based on the predicted value of the phase of the oscillation signal. ### Claim 13 (depends on 9) The method of claim 9, wherein the time-to-digital converter further comprises at least one switch circuit coupled between an input node of the one of the plurality of sample circuits and a node of the time-to-digital converter that is configured to supply the oscillation signal to the one of the plurality of sample circuits, and wherein de-activating at least one of the plurality of sample circuits comprises: controlling the switch circuit to block a propagation of the oscillation signal to the one of the plurality of sample circuits based on the predicted value of the phase of the oscillation signal. ### Claim 14 (depends on 9) A method for a digital phase-locked loop, comprising: operating a time-to-digital converter according to the method of claim 9; generating an output value of the time-to-digital converter that is indicative of a phase difference between the reference signal and the oscillation signal, wherein the oscillation signal is generated by a controlled oscillator within the digital phase-locked loop; calculating, based on the output value, a current value of the phase of the oscillation signal; and calculating, based on the current value of the phase of the oscillation signal, a predicted value of the phase of the oscillation signal. ### Claim 15 (depends on 14) The method of claim 14, wherein calculating the predicted value of the phase of the oscillation signal is further based on a frequency of the oscillation signal.