# US 10,768,533 B2 · Method and system for generating programmed defects for use in metrology measurements > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,768,533 B2 - Document ID: US10768533B2 - Status: Granted - Kind: B2 - Application number: 15/730,551 - Filed: 2017-10-11 - Published: 2018-04-26 - Granted: 2020-09-08 - Earliest claimed: 2016-10-20 - Assignees: KLA-Tencor Corporation - Applicants: KLA-Tencor Corporation - Inventors: Hong Xiao; Nadav Gutman - Web page: https://patentgrep.com/patent/US10768533B2 ## CPC - G03F 7/70633: {Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching} - G01N 21/9501: {Semiconductor wafers (manufacturing processes per se of semiconductor devices implementing a measuring step H10P74/20)} - G03F 7/70466: {Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature (stitching G03F7/70475)} - G03F 7/70683: {Mark designs} - H01J 37/28: with scanning beams {(H01J37/268, H01J37/292, H01J37/2955 take precedence)} - G06T 2207/30148: Semiconductor; IC; Wafer - H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects} - H10P 74/27: {Structural arrangements therefor} - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) - G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q) - H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A system for generating and implementing programmed defects includes a lithography tool configured to form a multi-pattern structure including a first array pattern and a second array pattern on a sample. The first array pattern or the second array pattern contains a programmed defect to differentiate the first array pattern from the second array pattern. The system includes a metrology tool configured to acquire one or more images of the first array pattern and the second array pattern having a field-of-view containing the programmed defect. The system includes a controller including one or more processors. The one or more processors are configured to receive the images of the first array pattern and the second array pattern from the metrology, and determine a metrology parameter associated with the first array pattern or the second array pattern. ## Claims ### Claim 1 A system comprising: a lithography tool configured to form a multi-pattern structure including a first periodic array pattern in a first layer and a second array pattern in a second layer on a sample, wherein at least one of the first array pattern in the first layer or the second array pattern in the second layer contains a programmed defect to change the pattern of the first array pattern relative to the second array pattern to differentiate the first array pattern from the second array pattern; a metrology tool configured to acquire one or more images of the first array pattern and the second array pattern having a field-of-view containing the programmed defect; and a controller including one or more processors, wherein the one or more processors are configured to cause the one or more processors to execute a set of program instructions contained in memory, wherein the set of program instructions are configured to cause the one or more processors to: receive the one or more images of the first array pattern and the second array pattern containing the programmed defect from the metrology tool; and determine one or more metrology parameters associated with at least one of the first array pattern and the second array pattern based on the one or more images of the first array pattern and the second array pattern containing the programmed defect. ### Claim 2 (depends on 1) The system of claim 1, wherein the determining one or more metrology parameters associated with at least one of the first array pattern and the second array pattern comprises: determining an overlay error between the first array pattern and the second array pattern. ### Claim 3 (depends on 1) The system of claim 1, wherein the determining one or more metrology parameters associated with at least one of the first array pattern and the second array pattern comprises: determining a critical dimension (CD) of at least one of the first array pattern and the second array pattern. ### Claim 4 (depends on 1) The system of claim 1, wherein the determining one or more metrology parameters associated with at least one of the first array pattern and the second array pattern comprises: determining critical dimension uniformity (CDU) of at least one of the first array pattern and the second array pattern. ### Claim 5 (depends on 1) The system of claim 1, wherein the programmed defect comprises: at least one of a protrusion defect, an intrusion defect, a pinching defect, a gap defect, a pinhole defect, a bending defect, or a bridging defect. ### Claim 6 (depends on 1) The system of claim 1, wherein the programmed defect is formed in at least one of a scribe-line area, a dummy-fill area, or a real device area of the sample. ### Claim 7 (depends on 1) The system of claim 1, wherein the lithography tool comprises: at least one of an extreme ultraviolet (EUV) lithography tool or an electron-beam lithography tool. ### Claim 8 (depends on 1) The system of claim 1, wherein the metrology tool comprises: a scanning electron microscopy (SEM) metrology tool. ### Claim 9 (depends on 1) The system of claim 1, wherein the sample comprises: a semiconductor wafer. ### Claim 10 A lithography tool comprising: an illumination source; a mask stage configured to secure one or more pattern masks; a sample stage configured to secure a sample; and a set of optics configured to direct illumination from the illumination source to the one or more pattern masks to project two or more patterns from the one or more pattern masks onto the sample, wherein the one or more pattern masks includes at least one array pattern containing one or more programmed defects, wherein the one or more pattern masks are configured to form a first array pattern in a first layer and a second array pattern in a second layer on the sample, wherein at least one of the first array pattern or the second array pattern contains a programmed defect to change the pattern of the first array pattern relative to the second array pattern to differentiate the first array pattern from the second array pattern. ### Claim 11 (depends on 10) The lithography tool of claim 10, further comprising: a controller. ### Claim 12 (depends on 11) The lithography tool of claim 11, wherein the controller is configured to determine one or more metrology parameters associated with at least one of the first array pattern and the second array pattern. ### Claim 13 (depends on 12) The lithography tool of claim 12, wherein the controller is further configured to determine an overlay error between the first array pattern and the second array pattern. ### Claim 14 (depends on 12) The lithography tool of claim 12, wherein the controller is further configured to determine a critical dimension (CD) of at least one of the first array pattern and the second array pattern. ### Claim 15 (depends on 12) The lithography tool of claim 12, wherein the controller is further configured to determine a critical dimension uniformity (CDU) of at least one of the first array pattern and the second array pattern. ### Claim 16 (depends on 10) The lithography tool of claim 10, wherein the programmed defect comprises: at least one of a protrusion defect, an intrusion defect, a pinching defect, a gap defect, a pinhole defect, a bending defect, or a bridging defect. ### Claim 17 (depends on 10) The lithography tool of claim 10, wherein the lithography tool forms the programmed defect in at least one of a scribe-line area, a dummy-fill area, or a real device area of the sample. ### Claim 18 (depends on 10) The lithography tool of claim 10, wherein the lithography tool comprises: at least one of an extreme ultraviolet (EUV) lithography tool or an electron-beam lithography tool. ### Claim 19 (depends on 10) The lithography tool of claim 10, wherein the sample comprises: a semiconductor wafer. ### Claim 20 A metrology tool comprising: an electron beam source configured to generate a primary electron beam; a sample stage configured to secure a sample; a set of electron-optical elements configured to direct at least a portion of the primary electron beam onto a portion of the sample; a detector assembly configured to detect electrons emanating from one or more portions of two or more array patterns disposed on the sample, wherein at least one of a first array pattern in a first layer or a second array pattern in a second layer of the two or more array patterns contains a programmed defect to change the pattern of the first array pattern relative to the second array pattern to differentiate the first array pattern from the second array pattern; and a controller including one or more processors, wherein the one or more processors are configured to cause the one or more processors to execute a set of program instructions contained in memory, wherein the set of program instructions are configured to cause the one or more processors to: receive image data associated with the two or more array patterns from the detector assembly; and determine one or more metrology parameters associated with the two or more array patterns based on the received image data. ### Claim 21 (depends on 20) The metrology tool of claim 20, wherein the controller is configured to determine one or more metrology parameters associated with at least one of the first array pattern and the second array pattern. ### Claim 22 (depends on 20) The metrology tool of claim 20, wherein the controller is further configured to determine an overlay error between the first array pattern and the second array pattern. ### Claim 23 (depends on 20) The metrology tool of claim 20, wherein the controller is further configured to determine a critical dimension (CD) of at least one of the first array pattern and the second array pattern. ### Claim 24 (depends on 20) The metrology tool of claim 20, wherein the controller is further configured to determine a critical dimension uniformity (CDU) of at least one of the first array pattern and the second array pattern. ### Claim 25 (depends on 20) The metrology tool of claim 20, wherein the programmed defect comprises: at least one of a protrusion defect, an intrusion defect, a pinching defect, a gap defect, a pinhole defect, a bending defect, or a bridging defect. ### Claim 26 (depends on 20) The metrology tool of claim 20, wherein the programmed defect is formed in at least one of a scribe-line area, a dummy-fill area, or a real device area of the sample. ### Claim 27 (depends on 20) The metrology tool of claim 20, wherein the metrology tool comprises: a scanning electron microscopy (SEM) metrology tool. ### Claim 28 (depends on 20) The metrology tool of claim 20, wherein the sample comprises: a semiconductor wafer. ### Claim 29 A metrology target comprising: a first array pattern formed in a first layer on a sample; and a second array pattern formed in a second layer on the sample, wherein at least one of the first array pattern or the second array pattern includes a programmed defect to change the pattern of the first array pattern relative to the second array pattern to differentiate the first array pattern from the second array pattern in one or more images of the metrology target. ### Claim 30 (depends on 29) The metrology target of claim 29, wherein the programmed defect comprises: at least one of a protrusion defect, an intrusion defect, a pinching defect, a gap defect, a pinhole defect, a bending defect, or a bridging defect. ### Claim 31 (depends on 29) The metrology target of claim 29, wherein the programmed defect is formed in at least one of a scribe-line area, a dummy-fill area, or a device area of the sample. ### Claim 32 (depends on 29) The metrology target of claim 29, wherein at least one of the first array pattern or the second array pattern comprise: a line array pattern. ### Claim 33 (depends on 29) The metrology target of claim 29, wherein at least one of the first array pattern or the second array pattern comprise: a two-dimensional array of pattern elements. ### Claim 34 (depends on 29) The metrology target of claim 29, wherein the first array pattern and the second array pattern are configured for measurement with a metrology tool. ### Claim 35 (depends on 34) The metrology target of claim 34, wherein the first array pattern and the second array pattern are configured for one or more overlay measurements with an imaging-based overlay metrology tool. ### Claim 36 (depends on 34) The metrology target of claim 34, wherein the first array pattern and the second array pattern are configured for one or more critical dimension uniformity measurements with a critical dimensional metrology tool. ### Claim 37 (depends on 34) The metrology target of claim 34, wherein the metrology tool comprises: a scanning electron microscopy (SEM) metrology tool. ### Claim 38 (depends on 29) The metrology target of claim 29, wherein the sample comprises: a semiconductor wafer.