# US 10,768,532 B2 · Co-optimization of lithographic and etching processes with complementary post exposure bake by laser annealing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,768,532 B2 - Document ID: US10768532B2 - Status: Granted - Kind: B2 - Application number: 15/980,501 - Filed: 2018-05-15 - Published: 2019-11-21 - Granted: 2020-09-08 - Earliest claimed: 2018-05-15 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Jing Sha; Ekmini Anuja De Silva; Nelson Felix; Derren Dunn - Web page: https://patentgrep.com/patent/US10768532B2 ## CPC - G03F 7/40: Treatment after imagewise removal, e.g. baking - G03F 7/7055: {Exposure light control in all parts of the microlithographic apparatus, e.g. pulse length control or light interruption} - G03F 1/44: Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales - G03F 7/168: {Finishing the coated layer, e.g. drying, baking, soaking} - G03F 7/202: {Masking pattern being obtained by thermal means, e.g. laser ablation} - G03F 7/70625: {Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness} - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) ## Abstract A method of co-optimizing lithographic and etching processes for semiconductor fabrication. The method includes determining a first set of locations for a first complementary laser annealing to be performed on. The first complementary laser annealing is performed at the first set of locations on at least a first semiconductor wafer of a plurality of semiconductor wafers. The first complementary laser annealing is performed before or after a first post-exposure baking process for the at least first semiconductor wafer. After an etching process has been performed on at least the first semiconductor wafer, a second set of locations is determined for a second complementary laser annealing to be performed on. The second complementary laser annealing is performed at the second set of locations on at least a second semiconductor wafer of the plurality of semiconductor wafers. The second complementary laser annealing is performed before or after a second post-exposure baking process. ## Claims ### Claim 1 A method of co-optimizing lithographic and etching processes for semiconductor fabrication, the method comprising: determining a first set of locations for a first complementary laser annealing to be performed on at least a first semiconductor wafer of a plurality of semiconductor wafers; after a first post-exposure baking process has been performed on at least the first semiconductor wafer, performing the first complementary laser annealing at the first set of locations on at least the first semiconductor wafer; after an etching process has been performed on at least the first semiconductor wafer, determining a second set of locations for a second complementary laser annealing to be performed on at least a second semiconductor wafer of the plurality of semiconductor wafers; and after a second post-exposure baking process has been performed on at least the second semiconductor wafer, performing the second complementary laser annealing at the second set of locations on at least the second semiconductor wafer. ### Claim 2 (depends on 1) The method of claim 1, wherein determining the first set of locations and performing the first complementary laser annealing are iteratively performed until a uniformity of critical dimension for features within one or more given areas of at least one semiconductor wafer of the plurality of semiconductor wafers satisfies at least a first uniformity of critical dimension threshold, and wherein determining the second set of locations and performing the second complementary laser annealing are iteratively performed after the at least first uniformity of critical dimension threshold has been satisfied and until a uniformity of critical dimension for features within one or more given areas of at least one semiconductor wafer of the plurality of semiconductor wafers satisfies at least a second uniformity of critical dimension threshold. ### Claim 3 (depends on 1) The method of claim 1, wherein determining the first set of locations comprises: analyzing uniformity of critical dimension for features within a given area of at least a third semiconductor wafer of the plurality of semiconductor wafers after a third post-exposure baking process and prior to an etching process; determining that the uniformity of critical dimension for the features fails to satisfy one or more uniformity of critical dimension thresholds; and selecting the first set of locations from the given area. ### Claim 4 (depends on 3) The method of claim 3, wherein the given area comprises: the third semiconductor as a whole; a plurality of fields within at least the third semiconductor wafer; or a single a field within at least the third semiconductor wafer. ### Claim 5 (depends on 3) The method of claim 3, wherein performing the first complementary laser annealing at the first set of locations of the at least second semiconductor wafer comprises: adjusting one or more operating parameters of the first complementary laser annealing based on determining the uniformity of critical dimension for the features fails to satisfy the one or more uniformity of critical dimension thresholds. ### Claim 6 (depends on 1) The method of claim 1, wherein determining the second set of locations comprises: analyzing uniformity of critical dimension for features within a given area of at least the first semiconductor wafer after the etching process; determining that the uniformity of critical dimension for the features fails to satisfy one or more uniformity of critical dimension thresholds; and selecting the second set of locations from the given area. ### Claim 7 (depends on 6) The method of claim 6, wherein the given area comprises: an entirety of at least the first semiconductor as a whole; a plurality of fields within at least the first semiconductor wafer; or a single a field within at least the first semiconductor wafer. ### Claim 8 (depends on 6) The method of claim 6, wherein performing the second complementary laser annealing at the second set of locations of the second semiconductor wafer comprises: adjusting one or more operating parameters of the second complementary laser annealing based on determining the uniformity of critical dimension for the features fails to satisfy the one or more uniformity of critical dimension thresholds. ### Claim 9 A method of co-optimizing lithographic and etching processes for semiconductor fabrication, the method comprising: determining a first set of locations for first complementary laser annealing to be performed on at least a first semiconductor wafer of a plurality of semiconductor wafers; prior to a first post-exposure baking process being performed on at least the first semiconductor wafer, performing the first complementary laser annealing at the first set of locations on at least the first semiconductor wafer; after an etching process has been performed on at least the first semiconductor wafer, determining, a second set of locations for a second complementary laser annealing to be performed on at least a second semiconductor wafer of the plurality of semiconductor wafers; and prior to a second post-exposure baking process being performed on at least the second semiconductor wafer, performing the second complementary laser annealing at the second set of locations on at least the second semiconductor wafer. ### Claim 10 (depends on 9) The method of claim 9, wherein determining the first set of locations and performing the first complementary laser annealing are iteratively performed until a uniformity of critical dimension for features within one or more given areas of at least one semiconductor wafer of the plurality of semiconductor wafers satisfies at least a first uniformity of critical dimension threshold, and wherein determining the second set of locations and performing the second complementary laser annealing are iteratively performed after the at least first uniformity of critical dimension threshold has been satisfied and until a uniformity of critical dimension for features within one or more given areas of at least one semiconductor wafer of the plurality of semiconductor wafers satisfies at least a second uniformity of critical dimension threshold. ### Claim 11 (depends on 10) The method of claim 10, wherein determining the first set of locations comprises: analyzing uniformity of critical dimension for features within a given area of at least a third semiconductor wafer after a third post-exposure baking process and prior to an etching process; determining that the uniformity of critical dimension for the features fails to satisfy one or more uniformity of critical dimension thresholds; and selecting the first set of locations from the given area. ### Claim 12 (depends on 11) The method of claim 11, wherein the given area comprises: an entirety at least the third semiconductor as a whole; a plurality of fields within at least the third semiconductor wafer; or a single a field within at least the third semiconductor wafer. ### Claim 13 (depends on 11) The method of claim 11, wherein performing the first complementary laser annealing at the first set of locations of at least the second semiconductor wafer comprises: adjusting one or more operating parameters of the first complementary laser annealing based on determining the uniformity of critical dimension for the features fails to satisfy the one or more uniformity of critical dimension thresholds. ### Claim 14 (depends on 10) The method of claim 10, wherein determining the second set of locations comprises: analyzing uniformity of critical dimension for features within a given area of at least the first semiconductor wafer after the etching process; determining that the uniformity of critical dimension for the features fails to satisfy one or more uniformity of critical dimension thresholds; and selecting the second set of locations from the given area. ### Claim 15 (depends on 14) The method of claim 14, wherein the uniformity of critical dimension is analyzed for at least one of: at least the first semiconductor wafer as a whole; between two or more fields of at least the first; or between features within a field of at least the first semiconductor wafer. ### Claim 16 (depends on 14) The method of claim 14, wherein performing the second complementary laser annealing at the second set of locations of at least the second semiconductor wafer comprises: adjusting one or more operating parameters of the complementary laser annealing based on determining the uniformity of critical dimension for the features fails to satisfy the one or more uniformity of critical dimension thresholds. ### Claim 17 A system for co-optimizing lithographic and etching processes for semiconductor fabrication, the system comprising: memory; one or more processors; and at least one controller configured to perform a method comprising determining a first set of locations for a first complementary laser annealing to be performed on at least a first semiconductor wafer of a plurality of semiconductor wafers; performing the first complementary laser annealing at the first set of locations on at least the first semiconductor wafer, wherein the first complementary laser annealing is performed one of before or after a first post-exposure baking process for at least the first semiconductor wafer; after an etching process has been performed on at least the first semiconductor wafer, determining, a second set of locations for a second complementary laser annealing to be performed on at least a second semiconductor wafer of the plurality of semiconductor wafers; and performing the second complementary laser annealing at the second set of locations on at least the second semiconductor wafer, wherein the second complementary laser annealing is performed one of before or after a second post-exposure baking process for at least the second semiconductor wafer. ### Claim 18 (depends on 17) The system of claim 17, wherein determining the first set of locations and performing the first complementary laser annealing are iteratively performed until a uniformity of critical dimension for features within one or more given areas of at least one semiconductor wafer of the plurality of semiconductor wafers satisfies at least a first uniformity of critical dimension threshold, and wherein determining the second set of locations and performing the second complementary laser annealing are iteratively performed after the at least first uniformity of critical dimension threshold has been satisfied and until a uniformity of critical dimension for features within one or more given areas of at least one semiconductor wafer of the plurality of semiconductor wafers satisfies at least a second uniformity of critical dimension threshold. ### Claim 19 (depends on 17) The system of claim 17, wherein determining the first set of locations comprises: analyzing uniformity of critical dimension for features within a given area of at least a third semiconductor wafer of the plurality of semiconductor layers after a third post-exposure baking process and prior to an etching process; determining that the uniformity of critical dimension for the features fails to satisfy one or more uniformity of critical dimension thresholds; and selecting the first set of locations from the given area. ### Claim 20 (depends on 17) The system of claim 17, wherein determining the second set of locations comprises: analyzing uniformity of critical dimension for features within a given area of the at least the first semiconductor wafer after the etching process; determining that the uniformity of critical dimension for the features fails to satisfy one or more uniformity of critical dimension thresholds; and selecting the second set of locations from the given area.