# US 10,768,232 B2 · ATE compatible high-efficient functional test

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- Number: US 10,768,232 B2
- Document ID: US10768232B2
- Status: Granted
- Kind: B2
- Application number: 15/649,747
- Filed: 2017-07-14
- Published: 2019-01-17
- Granted: 2020-09-08
- Earliest claimed: 2017-07-14
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Thomas Gentner; Jens Kuenzer; Cedric Lichtenau; Martin Padeffke
- Web page: https://patentgrep.com/patent/US10768232B2

## CPC

- G01R 31/31917: {Stimuli generation or application of test patterns to the device under test [DUT]}
- G01R 31/3181: Functional testing (G01R31/3177 takes precedence)
- G01R 31/31905: {Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture}
- G01R 31/31908: {Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns}
- G01R 31/31919: {Storing and outputting test patterns (G01R31/31924 takes precedence; arithmetic and random test patterns generator)}
- G06F 11/2236: {to test CPU or processors}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method, computer program product and/or system is disclosed. According to an aspect of this invention, a device under test (DUT) is switched to a functional test mode. In some embodiments of the present invention, the DUT receives a general scan design (GSD) pattern while in the functional test mode. In some embodiments, the DUT executes a first functional test corresponding to the GSD pattern. In yet other embodiments, the DUT further comprises a state machine that controls the execution of the first functional test. The DUT may further store the output address, the output data, and the status to an address register, a data register, and a status register, respectively and/or send the output address, the output data, and the status to an address register to an automatic testing equipment (ATE).

## Claims

### Claim 1

A method, comprising:
switching a device under test (DUT) to a functional test mode;
receiving, by the DUT, via a scan-in pin of a parallel scan design interface, a scan design pattern;
translating, by the DUT, the received scan design pattern into a first functional test, the first functional test having a first functional command, the received scan design pattern identifying of a part of the DUT to be tested by referencing an address register, and the received scan design pattern identifying data to be used by the first functional command as input by referencing a data register;
executing, by the DUT, the first functional test, wherein a state machine controls the execution of the first functional test; and
sending, by the DUT, via a scan-out pin of the parallel scan design interface, output data corresponding to the first functional test to an automatic test equipment.

### Claim 2 (depends on 1)

The method of claim 1, wherein the state machine further controls an output address corresponding to the execution of the first functional test, the output data corresponding to the first functional test, and a status corresponding to the first functional test.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
storing, by the DUT, the output address, the output data, and the status to the address register, the data register, and a status register, respectively; and
sending, by the DUT, via the scan-out pin of the parallel scan design interface, the output address and the status to the automatic test equipment.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
receiving, by the DUT, a second functional command via a services interface; and
executing, by the DUT, a second functional test corresponding to the received second functional command, wherein the state machine controls the execution of the second functional test.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
receiving, by the DUT, a second functional command via an inter-integrated circuit (I2C) interface; and
executing, by the DUT, a third functional test corresponding to the received second functional command, wherein the state machine controls the execution of the third functional test.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
further translating, by the DUT, the received scan design pattern into a second functional test, the second functional test having a second functional command and an identification of data to be used by the second functional command as input;
executing, by the DUT, the second functional test, wherein the state machine controls the execution of the second functional test; and
sending, by the DUT, via the scan-out pin of the parallel scan design interface, output data corresponding to the second functional test to the automatic test equipment;
wherein the receiving of the scan design pattern occurs via a single scan load.

### Claim 7

A computer program product comprising:
one or more computer readable storage media; and
program instructions stored on the one or more computer readable storage media, the stored program instructions comprising:
program instructions to switch a device under test (DUT) to a functional test mode;
program instructions to receive, via a scan-in pin of a parallel scan design interface, a scan design pattern;
program instructions to translate the received scan design pattern into a first functional test, the first functional test having a first functional command, the received scan design pattern identifying of a part of the DUT to be tested by referencing an address register, and the received scan design pattern identifying data to be used by the first functional command as input by referencing a data register;
program instructions to execute the first functional test, wherein a state machine controls the execution of the first functional test; and
program instructions to send, via a scan-out pin of the parallel scan design interface, output data corresponding to the first functional test to an automatic test equipment.

### Claim 8 (depends on 7)

The computer program product of claim 7, wherein the state machine further controls an output address corresponding to the execution of the first functional test, the output data corresponding to the first functional test, and a status corresponding to the first functional test.

### Claim 9 (depends on 8)

The computer program product of claim 8, the stored program instructions further comprising:
program instructions to store the output address, the output data, and the status the address register, the data register, and a status register, respectively; and
program instructions to send, via the scan-out pin of the parallel scan design interface, the output address and the status to the automatic test equipment.

### Claim 10 (depends on 7)

The computer program product of claim 7, the stored program instructions further comprising:
program instructions to receive a second functional command via a services interface; and
program instructions to execute a second functional test corresponding to the received second functional command, wherein the state machine controls the execution of the second functional test.

### Claim 11 (depends on 7)

The computer program product of claim 7, the stored program instructions further comprising:
program instructions to receive a second functional command via an inter-integrated circuit (I2C) interface; and
program instructions to execute a third functional test corresponding to the received second functional command, wherein the state machine controls the execution of the third functional test.

### Claim 12 (depends on 7)

The computer program product of claim 7, the stored program instructions further comprising:
program instructions to further translate the received scan design pattern into a second functional test, the second functional test having a second functional command and an identification of data to be used by the second functional command as input;
program instructions to execute the second functional test, wherein the state machine controls the execution of the second functional test; and
program instructions to send, via the scan-out pin of the parallel scan design interface, output data corresponding to the second functional test to the automatic test equipment;
wherein the receiving of the scan design pattern occurs via a single scan load.

### Claim 13

A computer system comprising:
one or more computer processors;
one or more computer readable media; and
program instructions, stored on the one or more computer readable media for execution by at least one of the one or more processors, the stored program instructions comprising:
program instructions to switch a device under test (DUT) to a functional test mode; program instructions to receive, via a scan-in pin of a parallel scan design interface, a scan design pattern;
program instructions to translate the received scan design pattern into a first functional test, the first functional test having a first functional command, the received scan design pattern identifying of a part of the DUT to be tested by referencing an address register, and the received scan design pattern identifying data to be used by the first functional command as input by referencing a data register;
program instructions to execute the first functional test, wherein a state machine controls the execution of the first functional test; and
program instructions to send, via a scan-out pin of the parallel scan design interface, output data corresponding to the first functional test to an automatic test equipment.

### Claim 14 (depends on 13)

The computer system of claim 13, wherein the state machine further controls an output address corresponding to the execution of the first functional test, the output data corresponding to the first functional test, and a status corresponding to the first functional test.

### Claim 15 (depends on 14)

The computer system of claim 14, the stored program instructions further comprising:
program instructions to store the output address, the output data, and the status to the address register, the data register, and a status register, respectively; and
program instructions to send, via the scan-out pin of the parallel scan design interface, the output address and the status to the automatic test equipment.

### Claim 16 (depends on 13)

The computer system of claim 13, the stored program instructions further comprising:
program instructions to receive a second functional command via a services interface; and
program instructions to execute a second functional test corresponding to the received second functional command, wherein the state machine controls the execution of the second functional test.

### Claim 17 (depends on 13)

The computer system of claim 13, the stored program instructions further comprising:
program instructions to receive a second functional command via an inter-integrated circuit (I2C) interface; and
program instructions to execute a third functional test corresponding to the received second functional command, wherein the state machine controls the execution of the third functional test.