# US 10,768,230 B2 · Built-in device testing of integrated circuits

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- Number: US 10,768,230 B2
- Document ID: US10768230B2
- Status: Granted
- Kind: B2
- Application number: 15/166,578
- Filed: 2016-05-27
- Published: 2017-11-30
- Granted: 2020-09-08
- Earliest claimed: 2016-05-27
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Robert M. Casatuta; Mary P. Kusko; Gary W. Maier; Franco Motika; Phong T. Tran
- Web page: https://patentgrep.com/patent/US10768230B2

## CPC

- G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)}
- G01R 31/31707: {Test strategies (methods for generation of test sequences G01R31/318371)}
- G01R 31/2834: {Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736)}
- G01R 31/2851: {Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801)}
- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/3183: Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R 31/318569: {Error indication, logging circuits}
- G01R 31/318594: {Timing aspects (clock circuits G01R31/318552)}
- G01R 31/3187: Built-in tests
- G01R 31/319: Tester hardware, i.e. output processing circuits
- G01R 31/31901: {Analysis of tester Performance; Tester characterization}
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 11/27: Built-in tests
- G06F 11/3672: {Test management}
- G06F 11/3692: {for test results analysis}
- G11C 29/12: Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details}
- G11C 29/4401: {for self repair}
- G11C 29/56008: {Error analysis, representation of errors}
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.

## Claims

### Claim 1

A method comprising:
loading an on-chip test flow and control testing program for execution by a microcontroller within a device under test;
causing the microcontroller within the device under test to execute the testing program, wherein the testing program is arranged to adjust one or more of any of the following parameters of the device under test: on-chip scan configuration, chip clock skew, voltage regulators, voltage pumps, level shifters, partial-good configurations, redundancy selections, OCCG (On Chip Clock Generators), PLLs (Phase Lock Loops), timing circuits, and elastic I/O DLLs (Chip Input/Output Driver & Receiver Delay Lock Loops;
receiving, by the microcontroller within the device under test, results from the testing program;
dynamically adjusting, by the microcontroller within the device under test, the testing program based on the results of the testing program, wherein dynamically adjusting the testing program comprises adjusting one or more of the following parameters of the device under test that are not accessible by external testers: on-chip scan configuration, chip clock skew, voltage regulators, voltage pumps, level shifters, partial-good configurations, redundancy selections, OCG (On Chip Clock Generators), PLLs (Phase Lock Loops), timing circuits, and elastic I/O DLLs (Chip Input/Output Driver & Receiver Delay Lock Loops) and wherein dynamically adjusting the testing program based on the results of the testing program comprises determining that a desired result was not achieved by the results of the testing program; and
causing the microcontroller within the device under test to execute the adjusted testing program.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
storing the results from the testing program in a test results memory located on the device under test.

### Claim 3 (depends on 1)

The method of claim 1 further comprising:
causing a self-repair of the device under test upon detection of a problem with the device under test.

### Claim 4 (depends on 1)

The method of claim 1 further comprising:
creating a shmoo plot based on results of the testing program.

### Claim 5 (depends on 1)

The method of claim 1 further comprising:
identifying portions of the device under test for further testing based on results of the testing program; and wherein:
dynamically adjusting the testing program comprises adjusting the testing program to test the identified portions of the device under test.

### Claim 6

A system comprising:
a memory;
a processor system communicatively coupled to the memory;
a device under test, the device under test comprising an adaptive testing microcontroller;
the adaptive testing microcontroller configured to perform a method comprising:
loading a testing program from the processor system;
executing the testing program, wherein the testing program is arranged to adjust one or more of the following parameters of the device under test: on-chip scan configuration, chip clock skew, voltage regulators, voltage pumps, level shifters, OCCG (On Chip Clock Generators), PLLs (Phase Lock Loops), timing circuits, and elastic I/O DLLs (Chip Input/Output Driver & Receiver Delay Lock Loops);
receiving, by the microcontroller within the device under test, results from the testing program;
wherein dynamically adjusting the testing program comprises adjusting one or more of the following parameters of the device under test that are not accessible by external testers: on-chip scan configuration, chip clock skew, voltage regulators, voltage pumps, level shifters, OCCG (On Chip Clock Generators), PLLs (Phase Lock Loops), timing circuits, and elastic I/O DLLs (Chip Input/Output Driver & Receiver Delay Lock Loops) and wherein dynamically adjusting the testing program based on the results of the testing program comprises determining that a desired result was not achieved by the results of the testing program; and
executing the adjusted testing program.

### Claim 7 (depends on 6)

The system of claim 6 further comprising:
storing the results from the testing program in a results memory located on the device under test.

### Claim 8 (depends on 6)

The system of claim 6 further comprising:
causing a self-repair of the device under test upon detection of a problem with the device under test.

### Claim 9 (depends on 6)

The system of claim 6 further comprising:
an analytical processor configured to analyze results of the execution of the testing program;
wherein the analytical processor is further configured to make cognitive decisions to redirect the adaptive testing microcontroller for more testing based on the results.

### Claim 10 (depends on 6)

The system of claim 6 further comprising:
identifying portions of the device under test for further testing based on results of the testing program; and wherein:
dynamically adjusting the testing program comprises adjusting the testing program to test the identified portions of the device under test.

### Claim 11

A computer program product comprising:
a computer-readable storage medium having program instructions embodied therewith, wherein the computer-readable storage medium is not a transitory signal, the program instructions readable by a processor system to cause the processor system to perform a method comprising:
loading a testing program from the processor system for execution by a microcontroller within a device under test;
executing, by the microcontroller within the device under test, the testing program, wherein the testing program is arranged to adjust one or more of the following parameters of the device under test: on-chip scan configuration, chip clock skew, voltage regulators, voltage pumps, level shifters, partial-good configurations, redundancy selections, OCG (On Chip Clock Generators), PLLs (Phase Lock Loops), timing circuits, and elastic I/O DLLs (Chip Input/Output Driver & Receiver Delay Lock Loops);
receiving results from the testing program;
dynamically adjusting, by the microcontroller within the device under test, the testing program based on the results of the testing program, wherein dynamically adjusting the testing program comprises adjusting one or more of the following parameters of the device under test that are not accessible by external testers: on-chip scan configuration, chip clock skew, voltage regulators, voltage pumps, level shifters, partial-good configurations, redundancy selections, OCG (On Chip Clock Generators), PLLs (Phase Lock Loops), timing circuits, and elastic I/O DLLs (Chip Input/Output Driver & Receiver Delay Lock Loops) and wherein dynamically adjusting the testing program based on the results of the testing program comprises determining that a desired result was not achieved by the results of the testing program; and
executing the adjusted testing program.

### Claim 12 (depends on 11)

The computer program product of claim 11 further comprising:
causing a self-repair of the device under test upon detection of a problem with the device under test.

### Claim 13 (depends on 11)

The computer program product of claim 11 further comprising:
creating a shmoo plot based on results of the testing program.

### Claim 14 (depends on 11)

The computer program product of claim 11 further comprising:
identifying portions of the device under test for further testing based on results of the testing program; and wherein:
dynamically adjusting the testing program comprises adjusting the testing program to test the identified portions of the device under test.

### Claim 15 (depends on 1)

The method of claim 1, wherein the device under test comprises an integrated circuit chip.

### Claim 16 (depends on 6)

The system of claim 6, wherein the device under test comprises an integrated circuit chip.

### Claim 17 (depends on 11)

The computer program product of claim 11, wherein the device under test comprises an integrated circuit chip.