# US 10,768,223 B2 ยท Semiconductor device and memory module including the semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server โ€” see https://patentgrep.com/llms.txt - Number: US 10,768,223 B2 - Document ID: US10768223B2 - Status: Granted - Kind: B2 - Application number: 16/213,771 - Filed: 2018-12-07 - Published: 2019-11-28 - Granted: 2020-09-08 - Earliest claimed: 2018-05-23 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Yong Seop Kim - Web page: https://patentgrep.com/patent/US10768223B2 ## CPC - G01R 31/2853: {Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66)} - G11C 29/025: {in signal lines} - G01R 31/31813: {Test pattern generators} - G01R 31/318513: {Test of Multi-Chip-Moduls} - G11C 29/26: Accessing multiple arrays (G11C29/24 takes precedence) - G11C 29/42: using error correcting codes [ECC] or parity check - G11C 29/50008: {of impedance} - G11C 29/56004: {Pattern generation} - G11C 29/56008: {Error analysis, representation of errors} - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 2029/2602: {Concurrent test} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor device may include a plurality of chips and a test pad. The plurality of chips may check parity bits of a plurality of pattern signals activated in units of specific bits and store test result signals generated by the checking of the parity bits. The plurality of chips may output an error detection signal when an error is detected from any of the test result signals. The test pad may output the error detection signal received from the plurality of chips to an external part. The plurality of chips may be commonly coupled to at least one connection line such that, when the error detection signal is output from at least one of the plurality of chips, the outputted error detection signal s output through the test pad. ## Claims ### Claim 1 A semiconductor device comprising: a plurality of chips configured to check parity bits of a plurality of pattern signals and store test result signals generated by the checking of the parity bits, and configured to output an error detection signal when an error is detected from any of the test result signals; and a test pad configured to output the error detection signal received from the plurality of chips to an external part, wherein the plurality of chips is commonly coupled to at least one connection line such that, when the error detection signal is output from at least one of the plurality of chips, the outputted error detection signal is output through the test pad, wherein the plurality of pattern signals include a predetermined number of activated bits, wherein each of the plurality of chips includes: a buffer circuit configured to buffer a command, an address, at least one chip ID signal, and a chip selection signal, and configured to output the plurality of pattern signals in response to a test signal; a parity check circuit configured to output the test result signals and the error detection signal by checking parity bits of the plurality of pattern signals; a storage circuit configured to store the test result signals therein; and a register configured to store an output signal of the storage circuit, and output stored test information to an external part during a read operation. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the error detection signal is output in response to a result of testing connectivity of the connection line. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of chips is configured to receive a first portion of the address through a first connection line that is commonly connected, and configured to receive the command and a remaining portion of the address other than the first portion of the address through a second connection line that is commonly connected. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of chips is configured to commonly receive the at least one chip ID signal, the test signal, and the chip selection signal. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of chips is configured to determine the presence or absence of an error by checking whether the number of activated parity bits from among the plurality of pattern signals is an even number. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the buffer circuit includes: a first buffer configured to buffer the command, the address, and the at least one chip ID signal; a second buffer configured to buffer the chip selection signal; a first delay circuit configured to output a delay signal by delaying an output signal of the first buffer; a second delay circuit configured to output a delay selection signal by delaying an output signal of the second buffer; and a latch circuit configured to latch the delay signal in response to the delay selection signal during activation of the test signal, and output the plurality of pattern signals. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the parity check circuit is configured to detect the error by checking whether the number of logic values of โ€œ1โ€ from among parity bits of the plurality of pattern signals is an even number. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the parity check circuit includes: a parity circuit configured to output the test result signals by logically combining parity bits of the plurality of pattern signals; and a test result output circuit configured to activate the error detection signal when the error is detected from the test result signals, and output the activated error detection signal. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the storage circuit includes: a plurality of log information latches configured to store information regarding an erroneous pattern signal from among the plurality of pattern signals in response to the test result signals. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the register is configured to store information regarding the test result signals, and include a multi-purpose register (MPR) that outputs the stored information as predetermined pattern data during activation of a read signal. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of chips is configured in a manner that a test result from the register for each chip is output in response to at least one chip ID signal during a read operation. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of pattern signals is generated by the command, the address, and the at least one chip ID signal, wherein the command, the address, and the at least one chip ID signal include an even number of activated bits. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of pattern signals is synchronized with a chip selection signal such that the pattern signals include the predetermined number of simultaneously activated bits. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of chips is configured to receive the pattern signal including the predetermined number of activated bits as a first logic level, and receive the remaining pattern signals other than the received pattern signal as a second logic level. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein patterns of the plurality of pattern signals change according to a combination of any two signals from among the command, the address, and the at least one chip ID signal, and wherein the plurality of pattern signals are received by the plurality of chips. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, wherein the connection line includes any one of a through silicon via (TSV) and wire bonding. ### Claim 17 A memory module comprising: a controller configured to generate a plurality of pattern signals include a predetermined number of activated bits; and a semiconductor device configured to check parity bits of a plurality of pattern signals and store test result signals generated by the checking of the parity bits, and configured to output an error detection signal when an error is detected from any of the test result signals, wherein the semiconductor device includes a plurality of chips commonly coupled to at least one connection line such that, when the error detection signal is output from at least one of the plurality of chips, the outputted error detection signal is output through a test pad, wherein each of the plurality of chips includes: a buffer circuit configured to buffer a command, an address, at least one chip ID signal, and a chip selection signal, and configured to output the plurality of pattern signals in response to a test signal; a parity check circuit configured to output the test result signals and the error detection signal by checking parity bits of the plurality of pattern signals; a storage circuit configured to store the test result signals therein; and a register configured to store an output signal of the storage circuit, and output stored test information to an external part during a read operation. ### Claim 18 (depends on 17) The memory module according to claim 17, wherein the controller includes: a test control circuit configured to generate a test command for testing a defect of each connection line of the semiconductor device; and a test pattern generation circuit configured to change the plurality of pattern signals in response to the test command, and output the changed pattern signals. ### Claim 19 (depends on 17) The memory module according to claim 17, wherein the plurality of chips is simultaneously tested by a test signal such that test results of the respective chips are output in response to at least one chip ID signal.