# US 10,768,222 B1 · Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structure

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- Number: US 10,768,222 B1
- Document ID: US10768222B1
- Status: Granted
- Kind: B1
- Application number: 15/997,411
- Filed: 2018-06-04
- Granted: 2020-09-08
- Earliest claimed: 2017-06-02
- Assignees: PDF Solutions, Inc.
- Applicants: PDF Solutions, Inc.
- Inventors: Tomasz Brozek
- Web page: https://patentgrep.com/patent/US10768222B1

## CPC

- G01R 31/2853: {Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66)}
- G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G11C 29/025: {in signal lines}
- G11C 29/1201: {comprising I/O circuitry}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Described here is an apparatus and method of testing a vertical (3D) semiconductor memory structure coupled between word lines and bit lines, by means of a direct connections of a plurality of test pads to word lines and bit lines of the memory structure on memory product wafer. Such connections are created by modified patterns of metal lines through contacts and vias created on the memory product wafer. The described apparatus and method are used for detecting electrical continuity (opens and shorts) in the memory structure, calculating resistance of selected word lines or bit cell strings, or performing more complex tests of memory bit cell transistors. The result of this detection can then be used to find defective regions or memory cells in the semiconductor memory structure. Such a testing device may be referred to as a direct testing system.

## Claims

### Claim 1

A method for testing a vertical memory structure disposed on a semiconductor substrate, the method comprising:
creating, from a wafer containing a plurality of 3D memory devices, including at least one direct connect 3D memory device;
wherein some of the plurality of 3D memory devices include peripheral circuitry interconnects disposed over a first 3D memory structure comprising strings of memory cells arranged in an array and coupled between word lines and bit lines;
wherein the at least one direct connect 3D memory device has no peripheral circuitry interconnects, and is disposed over a second 3D memory structure constructed the same as the first 3D memory structure comprising the strings of memory cells arranged in the array and coupled between the word lines and the bit lines of the some of the plurality of 3D memory devices;
wherein the step of creating includes providing a testing interconnect structure including test pads over the second 3D memory structure of the at least one direct connect 3D memory device that allows direct electrical connections to the word lines and the bit lines associated therewith;
directly connecting a direct tester to predetermined ones of the test pads of the at least one direct connect 3D memory device; and
using the direct tester, applying a predetermined voltage to the at least one direct connect 3D memory device to test the electrical integrity of the second 3D memory structure of the at least one direct connect 3D memory device.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the electrical integrity is one of an open, a short and a leakage of at least one memory cell in the second 3D memory structure.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the direct tester is used to further test resistance and capacitance of at least one memory cell in the second 3D memory structure.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the direct tester is further used to test threshold voltage and conductance of at least one memory cell in the second 3D memory structure.

### Claim 5 (depends on 4)

The method of claim 4, wherein the direct tester tests multiple ones of the memory cells in the second 3D memory structure in parallel.

### Claim 6 (depends on 5)

The method of claim 5, wherein at least 128 memory cells are tested in parallel.

### Claim 7 (depends on 1)

The method of claim 1, wherein the direct tester tests multiple ones of the memory cells in the second 3D memory structure in parallel.

### Claim 8 (depends on 7)

The method of claim 7, wherein at least 128 memory cells are tested in parallel.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the step of using the tester includes parallel testing with connections made to certain ones of the test pads across the array of the second 3D memory structure to allow detection of a particular failure mode and enable localization of the failure.

### Claim 10 (depends on 1)

The method according to claim 1, wherein the step of using the tester includes overstressing or applying prolonged or cyclical test under various conditions to at least one memory cell in the second 3D memory structure.

### Claim 11 (depends on 10)

The method according to claim 10, wherein the step of using the tester includes parallel testing with connections made to certain ones of the test pads across the array of the 3D memory cells to allow detection of a particular failure mode and enable localization of the failure.

### Claim 12 (depends on 10)

The method according to claim 10, wherein the step of using the tester includes overstressing or applying prolonged or cyclical test under various conditions to at least one memory cell in the 3D memory structure.

### Claim 13

A method for testing a vertical memory structure disposed on a semiconductor substrate, the method comprising:
creating, from a wafer containing a plurality of 3D memory devices, at least one direct connect 3D memory device;
wherein the at least one direct connect 3D memory device has no peripheral circuitry interconnects, disposed over a 3D memory structure comprising strings of memory cells arranged in an array and coupled between word lines and bit lines;
wherein the step of creating includes providing a test interconnect structure including test pads over the 3D memory structure of the at least one direct connect 3D memory device that allows direct electrical connections to the word lines and the bit lines associated therewith;
directly connecting a direct tester to predetermined ones of the test pads of the at least one direct connect 3D memory device; and
using the direct tester, applying a predetermined voltage to the at least one direct connect 3D memory device to test the electrical continuity among the word lines and the bit lines of the at least one direct connect 3D memory device.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the electrical integrity is one of an open, a short and a leakage of at least one memory cell in the 3D memory structure.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the direct tester is used to further test resistance and capacitance of at least one memory cell in the 3D memory structure.

### Claim 16 (depends on 15)

The method according to claim 15, wherein the direct tester is further used to test threshold voltage and conductance of at least one memory cell in the 3D memory structure.

### Claim 17 (depends on 16)

The method of claim 16, wherein the direct tester tests multiple ones of the memory cells in the 3D memory structure in parallel.

### Claim 18 (depends on 17)

The method of claim 17, wherein at least 128 memory cells are tested in parallel.

### Claim 19 (depends on 13)

The method of claim 13, wherein the direct tester tests multiple ones of the memory cells in the 3D memory structure in parallel.

### Claim 20 (depends on 19)

The method of claim 19, wherein at least 128 memory cells are tested in parallel.