# US 10,768,218 B2 · Mismatch detection using replica circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,768,218 B2 - Document ID: US10768218B2 - Status: Granted - Kind: B2 - Application number: 16/206,828 - Filed: 2018-11-30 - Published: 2019-04-18 - Granted: 2020-09-08 - Earliest claimed: 2014-05-07 - Assignees: pSemi Corporation - Applicants: pSemi Corporation - Inventors: Dan William Nobbe; Ronald Eugene Reedy; Peter Bacon; James S. Cable - Web page: https://patentgrep.com/patent/US10768218B2 ## CPC - G01R 31/28: Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits G01R31/002;} testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers {or computer components} G06F11/00; checking static stores for correct operation G11C29/00 {; testing receivers or transmitters of transmission systems H04B17/00}) - G01R 31/2836: {Fault-finding or characterising (G01R31/2822 - G01R31/2831 take precedence)} - H03F 1/0277: {Selecting one or more amplifiers from a plurality of amplifiers} - H03F 1/223: {with MOSFET's} - H03F 1/56: Modifications of input or output impedances, not otherwise provided for - H03F 1/565: {using inductive elements} - H03F 3/193: with field-effect devices (H03F3/195 takes precedence) - H03F 3/195: in integrated circuits - H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)} - H03F 3/213: in integrated circuits - H03F 3/245: {with semiconductor devices only} - H03F 3/72: Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal - H03H 7/38: Impedance-matching networks - H04B 1/44: Transmit/receive switching - H04B 1/48: in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter {(H04B1/46 takes precedence)} - H03F 2200/102: A non-specified detector of a signal envelope being used in an amplifying circuit - H03F 2200/105: A non-specified detector of the power of a signal being used in an amplifying circuit - H03F 2200/222: A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier - H03F 2200/378: A variable capacitor being added in the output circuit, e.g. collector, drain, of an amplifier stage - H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2200/453: Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit - H03F 2200/456: A scaled replica of a transistor being present in an amplifier - H03F 2200/471: the voltage being sensed - H03F 2200/61: the cascode amplifier has more than one common gate stage - H03F 2203/21142: Output signals of a plurality of power amplifiers are parallel combined to a common output - H03F 2203/7236: the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es) - H04B 17/11: for calibration - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H03F: AMPLIFIERS - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H04B: TRANSMISSION ## Abstract An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic. ## Claims ### Claim 1 A circuital arrangement, comprising: a sensing circuit; a first radio frequency (RF) path coupled, through one or more sensing points of the first RF path, to the sensing circuit, the first RF path comprising a first active circuit; and a second RF path coupled through one or more sensing points of the second RF path to the sensing circuit, the second RF path comprising a second active circuit that is a reduced size replica of the first active circuit, wherein the sensing circuit is adapted to sense a difference between one or more operating characteristics of the first RF path, sensed at the one or more sensing points of the first RF path, and one or more reference operating characteristics of the second RF path, sensed at the one or more sensing points of the second RF path, the one or more operating characteristics of the first RF path are affected by a set of operating variables, the second RF path is configured so that one or more reference operating characteristics of the second RF path are substantially isolated from a subset of the operating variables, and the set of operating variables comprises one or more of: a) a load to the first/second RF paths, b) a local temperature at the first/second active circuits, c) hot carrier injection (HCI) effect on devices of the first/second active circuits, d) transient effects on the first/second active circuits, e) floating body effects on devices of the first/second active circuits, f) different operating modes of the first/second RF paths, or g) different frequencies of operation of the first/second RF paths. ### Claim 2 (depends on 1) The circuital arrangement according to claim 1, wherein: the first RF path is configured to transmit an RF signal at an output node of the first RF path through a matching impedance coupled to the output node of the first RF path, and the second RF path is configured to terminate an RF signal at an output node of the second RF path through a terminating impedance coupled to the output node of the second RF path. ### Claim 3 (depends on 2) The circuital arrangement according to claim 2, wherein the output node of the first RF path is coupled to the output node of the second RF path to combine the RF signal of the second RF path with the transmitted RF signal. ### Claim 4 (depends on 2) The circuital arrangement according to claim 2, wherein the output node of the first RF path is isolated from the output node of the second RF path. ### Claim 5 (depends on 2) The circuital arrangement according to claim 2, wherein a bandwidth of the terminating impedance is broader than a bandwidth of the matching impedance. ### Claim 6 (depends on 2) The circuital arrangement according to claim 2, wherein an impedance seen at the output node of the first RF path varies according to one or more operating variables of the set of operating variables. ### Claim 7 (depends on 6) The circuital arrangement according to claim 6, wherein variation of the impedance seen at the output node of the first RF path is in correspondence of a variation in operating characteristics of elements configured to be coupled to the output node. ### Claim 8 (depends on 7) The circuital arrangement according to claim 7, wherein the elements comprise one or more of: a) a filter, b) a matching circuit, c) a switch, and d) an antenna. ### Claim 9 (depends on 1) The circuital arrangement according to claim 1, wherein the first RF path and the second RF path each further comprise a signal processing circuit coupled to a respective input node or output node of the first active circuit and the second active circuit, wherein the signal processing circuit is configured to affect one or more of: a) a signal amplitude, b) a signal phase, and c) an impedance presented to the respective input node and output node, and wherein the signal processing circuit is adapted to be controlled by control signals that are based on signals sensed by the sensing circuit. ### Claim 10 (depends on 9) The circuital arrangement according to claim 9, wherein the signal processing circuit comprises one or more of: a) a tunable match circuit, b) a fixed match, c) a variable attenuator, d) a fixed attenuator, e) a variable phase shifter circuit, and f) a filter. ### Claim 11 (depends on 10) The circuital arrangement according to claim 10, wherein the signal processing circuit comprises one or more of a) a digital tunable capacitor (DTC), and b) a digital tunable inductor (DTL). ### Claim 12 (depends on 1) The circuital arrangement according to claim 1, wherein: the first RF path and the second RF path each comprises a biasing circuit configured to bias a respective one of the first active circuit and the second active circuit based on signals sensed by the sensing circuit. ### Claim 13 (depends on 12) The circuital arrangement according to claim 12, wherein the biasing circuit comprises gate biasing circuits to bias transistors of the respective one of the first active circuit and the second active circuit. ### Claim 14 (depends on 13) The circuital arrangement according to claim 13, wherein: the transistors of the respective one of the first active circuit and the second active circuit are arranged according to a cascode stack, and the gate biasing circuits comprise gate capacitors coupled to the transistors configured to evenly distribute an RF output voltage across the transistors. ### Claim 15 (depends on 1) The circuital arrangement according to claim 1, wherein the first RF path and the second RF path operate according to an efficiency improvement scheme. ### Claim 16 (depends on 15) The circuital arrangement according to claim 15, wherein the efficiency improvement scheme comprises one of: a) an envelope tracking scheme, b) an average power tracking scheme, c) a Doherty amplification scheme, and d) a linear amplification using nonlinear components (LINC) scheme. ### Claim 17 (depends on 1) The circuital arrangement according to claim 1, wherein the circuital arrangement is monolithically integrated in an integrated circuit either partially or in its entirety, according to a CMOS process comprising one of: a) a silicon-on-insulator (SOI) process, b) a silicon-on-sapphire process (SOS), and c) a bulk-silicon process. ### Claim 18 (depends on 17) The circuital arrangement according to claim 17, wherein the second active circuit is physically placed away from the first active circuit so as to exclude effect of a temperature of the first active circuit over the second active circuit. ### Claim 19 (depends on 17) The circuital arrangement according to claim 17, wherein the second active circuit is physically placed close to, or within, an area of the integrated circuit used by the first active circuit so as the first active circuit and the second active circuit are affected by a same temperature. ### Claim 20 (depends on 1) The circuital arrangement according to claim 1, wherein each of the first RF path and the second RF path comprise at least one RF switch. ### Claim 21 A circuital arrangement, comprising: a sensing circuit; a first radio frequency (RF) path coupled, through one or more sensing points of the first RF path, to the sensing circuit, the first RF path comprising a first active circuit; and a second RF path coupled through one or more sensing points of the second RF path to the sensing circuit, the second RF path comprising a second active circuit that is a reduced size replica of the first active circuit, wherein the sensing circuit is adapted to sense a difference between one or more operating characteristics of the first RF path, sensed at the one or more sensing points of the first RF path, and one or more reference operating characteristics of the second RF path, sensed at the one or more sensing points of the second RF path, wherein the circuital arrangement is monolithically integrated in an integrated circuit either partially or in its entirety, according to a CMOS process comprising one of: a) a silicon-on-insulator (SOI) process, b) a silicon-on-sapphire process (SOS), and c) a bulk-silicon process, and wherein the second active circuit is physically placed away from the first active circuit so as to exclude effect of a temperature of the first active circuit over the second active circuit.