# US 10,766,769 B2 · Semiconductor element and methods for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,766,769 B2 - Document ID: US10766769B2 - Status: Granted - Kind: B2 - Application number: 15/928,275 - Filed: 2018-03-22 - Published: 2018-07-26 - Granted: 2020-09-08 - Earliest claimed: 2015-02-25 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Christian Bretthauer; Dirk Meinhold - Web page: https://patentgrep.com/patent/US10766769B2 ## CPC - B81C 1/00904: {Multistep processes for the separation of wafers into individual elements not provided for in groups B81C1/00873 - B81C1/00896} - B81C 1/00063: {Trenches} - B81B 1/002: {Holes characterised by their shape, in either longitudinal or sectional plane} - B81B 2201/0264: Pressure sensors - B81B 2207/015: the micromechanical device and the control or processing electronics being integrated on the same substrate - B81B 2207/07: Interconnects - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) - B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00) ## Abstract A semiconductor element includes a processed substrate arrangement including a processed semiconductor substrate and a metallization layer arrangement on a main surface of the processed semiconductor substrate. The semiconductor element further includes a passivation layer arranged at an outer border of the processed substrate arrangement. ## Claims ### Claim 1 A semiconductor element comprising: a processed substrate arrangement comprising a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate; a passivation layer arranged at an outer border of the processed substrate arrangement; a microelectromechanical system (MEMS) functional element arranged at the processed semiconductor substrate; and a notch formed in the metallization layer structure, wherein the passivation layer is deposited such that the MEMS functional element, arranged at the processed semiconductor substrate in the notch, and side wall structures of the notch in the metallization layer structure are covered by the passivation layer, and wherein the metallization layer structure includes a kerf at a separation region in the processed semiconductor substrate, the separation region defining a border between a die region of the processed substrate arrangement and at least a second region of the processed substrate arrangement. ### Claim 2 (depends on 1) The semiconductor element according to claim 1, wherein the MEMS functional element is a MEMS sensor, a MEMS actuator, or a MEMS transducer. ### Claim 3 (depends on 1) The semiconductor element according to claim 1, wherein the MEMS functional element is arranged at the processed semiconductor substrate in the die region. ### Claim 4 (depends on 3) The semiconductor element according to claim 3, wherein the MEMS functional element is released from the metallization layer structure by a notch in the metallization layer structure. ### Claim 5 (depends on 4) The semiconductor element according to claim 4, wherein the passivation layer is arranged at the outer border of the processed substrate arrangement and at a side wall structure of the notch such that at least a portion of the MEMS functional element is exposed. ### Claim 6 (depends on 5) The semiconductor element according to claim 5, wherein the passivation layer is arranged at the outer border of the processed substrate arrangement and at a side wall structure of the kerf such that at least a portion of the main surface of processed substrate arrangement at the kerf is exposed. ### Claim 7 (depends on 5) The semiconductor element according to claim 5, wherein the passivation layer is arranged at the outer border of the processed substrate arrangement, at a side wall structure of the kerf, and at a bottom of the kerf such that the main surface of processed substrate arrangement at the kerf is entirely covered by the passivation layer. ### Claim 8 (depends on 1) The semiconductor element according to claim 1, wherein the passivation layer is arranged at the outer border of the processed substrate arrangement and at a side wall structure of the kerf such that at least a portion of the main surface of processed substrate arrangement at the kerf is exposed. ### Claim 9 (depends on 1) The semiconductor element according to claim claim 1, wherein the passivation layer is arranged at the outer border of the processed substrate arrangement, at a side wall structure of the kerf, and at a bottom of the kerf such that the main surface of processed substrate arrangement at the kerf is entirely covered by the passivation layer. ### Claim 10 (depends on 1) The semiconductor element according to claim 1, wherein the passivation layer comprises an insulator material comprising a silicon nitride material. ### Claim 11 (depends on 1) The semiconductor element according to claim 1, wherein the processed substrate arrangement comprises a breaking edge at the outer border. ### Claim 12 A semiconductor element, comprising: a processed substrate arrangement comprising a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate; a passivation layer arranged at an outer border of the processed substrate arrangement; and a microelectromechanical system (MEMS) functional element arranged at the processed semiconductor substrate, wherein the metallization layer structure includes a kerf at a separation region in the processed semiconductor substrate, the separation region defining a border between a die region of the processed substrate arrangement and at least a second region of the processed substrate arrangement, wherein the MEMS functional element is arranged at the processed semiconductor substrate in the die region, wherein the MEMS functional element is released from the metallization layer structure by a notch in the metallization layer structure, and wherein the passivation layer is arranged at the outer border of the processed substrate arrangement, at a side wall structure of the notch, and over a surface of the MEMS functional element such that at least a portion of the MEMS functional element is exposed. ### Claim 13 (depends on 12) The semiconductor element according to claim 12, wherein the passivation layer is arranged at the outer border of the processed substrate arrangement and at a side wall structure of the kerf such that at least a portion of the main surface of processed substrate arrangement at the kerf is exposed. ### Claim 14 (depends on 12) The semiconductor element according to claim 12, wherein the passivation layer is arranged at the outer border of the processed substrate arrangement, at a side wall structure of the kerf, and at a bottom of the kerf such that the main surface of processed substrate arrangement at the kerf is entirely covered by the passivation layer. ### Claim 15 A semiconductor element, comprising a processed substrate arrangement comprising a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate; a passivation layer arranged at an outer border of the processed substrate arrangement; and a microelectromechanical system (MEMS) functional element arranged at the processed semiconductor substrate, wherein the metallization layer structure includes a kerf at a separation region in the processed semiconductor substrate, the separation region defining a border between a die region of the processed substrate arrangement and at least a second region of the processed substrate arrangement, wherein the MEMS functional element is arranged at the processed semiconductor substrate in the die region, wherein the MEMS functional element is released from the metallization layer structure by a notch in the metallization layer structure, and wherein the passivation layer is arranged at the outer border of the processed substrate arrangement, at a side wall structure of the notch, and over a surface of the MEMS functional element such that the entire surface of the MEMS functional element is covered by the passivation layer. ### Claim 16 (depends on 15) The semiconductor element according to claim 15, wherein the passivation layer is arranged at the outer border of the processed substrate arrangement and at a side wall structure of the kerf such that at least a portion of the main surface of processed substrate arrangement at the kerf is exposed. ### Claim 17 (depends on 15) The semiconductor element according to claim 15, wherein the passivation layer is arranged at the outer border of the processed substrate arrangement, at a side wall structure of the kerf, and at a bottom of the kerf such that the main surface of processed substrate arrangement at the kerf is entirely covered by the passivation layer.