Input termination circuits for high speed receivers
AssigneeInphi Corporation
InventorsSimon Forey, Rajasekhar Nagulapalli, Parmanand Mishra
Life of this patent
Estimating the term…
Abstract
The present invention is directed to communication systems and electrical circuits. According to an embodiment, an input termination circuit includes a first attenuation resistor and a second attenuation resistor. The resistance values of these two resistors are adjusted in opposite directions to maintain a stable output impedance. There are other embodiments as well.
Claims20
A receiver apparatus comprising:
- an input termination circuit comprising:
- a first inductor connected to an input terminal;
- a first input resistor connected to the first inductor;
- a second inductor connected to the first input resistor;
- a first attenuation resistor connected to the first input resistor and the second inductor, the first attenuation resistor being adjustable by a first control signal;
- an output inductor connected to the second inductor;
- a second attenuation resistor connected to the second inductor and the output inductor, the second attenuation resistor being adjustable by a second control signal;
- an equalizer coupled to the output inductor;
- and
- an amplifier coupled to the equalizer.
A method of adjusting an input termination circuit, wherein the input termination circuit comprising a first attenuation resistor and a second attenuation resistor, the method comprising:
- initiating attenuation parameters associated with the input termination circuit, the attenuation parameters including a first resistance value associated with the first attenuation resistor and a second resistance value associated with the second attenuation resistor;
- adjusting the first resistance value based at least on a strength of data signals;
- adjusting the second resistance value based at least on the first resistance value;
- determining a bandwidth associated with the input termination circuit;
- adjusting the second resistance value based on the bandwidth and the strength of the data signals;
- and
- receiving the data signals using the input termination circuit.
A receiver apparatus comprising:
- an input termination circuit comprising:
- a first inductor connected to an input terminal;
- a first input resistor connected to the first inductor;
- a second inductor connected to the first input resistor;
- a first attenuation resistor connected to the first input resistor and the second inductor, the first attenuation resistor being adjustable by a first control signal;
- a first output inductor connected to the second inductor, the output inductor being adjustable to match input capacitance;
- a second attenuation resistor connected to the second inductor and the output inductor, the second attenuation resistor being adjustable by a second control signal;
- and
- an equalizer coupled to the output inductor, the equalizer being associated with an input capacitance.
Dependencies are inferred from the claim text.