Memory system that carries out soft bit decoding

Abstract

A memory system includes a nonvolatile semiconductor memory and a controller. The controller is configured to maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and carry out decoding of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order.

Dependencies are inferred from the claim text.