US 10,763,879 B1 · Low power and high-speed circuit for generating asynchronous clock signals

Abstract

Apparatus and associated methods relate to a clock generation circuit which generates asynchronous clock signals for a successive approximation ADC architecture based on time-interleaved comparators. In an illustrative example, a circuit may include (a) a first comparator configured to receive an input signal and generate a first ready signal to indicate a comparison decision being complete, (b) a second comparator configured to receive the input signal and generate a second ready signal to indicate a comparison decision being complete, and (c) a clock generation circuit coupled to receive the first and the second ready signals and generate a first clock for the first comparator and a second clock for the second comparator. The first and the second clock signals may be in anti-phase. Thus, each comparator may have enough time to reach a valid comparison in each successive approximation cycle, and kickback noises at comparator' inputs may be advantageously reduced.

Claims16

Dependent claims

A circuit, comprising:

a first comparator configured to receive an input signal and generate a first ready signal to indicate a comparison decision being complete;
a second comparator configured to receive the input signal and generate a second ready signal to indicate a comparison decision being complete;
and,
a clock generation circuit configured to receive the first ready signal and the second ready signal and generate a first clock signal for the first comparator and a second clock signal for the second comparator,
wherein, rising edges and falling edges of the first clock signal are substantially aligned with falling edges and rising edges of the second clock signal, respectively and wherein the clock generation circuit is configured to receive a first stop signal to stop the generation of the first clock signal, and the clock generation circuit is further configured to receive a second stop signal to stop the generation of the second clock signal, wherein the first stop signal and the second stop signal are independently controllable.

2 more elements

Dependencies are inferred from the claim text.

Low power and high-speed circuit for generating asynchronous clock signals

Life of this patent

Low power and high-speed circuit for generating asynchronous clock signals

Life of this patent

Abstract

Claims16