Digital fractional clock synthesizer with period modulation
AssigneeXilinx, Inc.
InventorsJulian Haines, Rhona Wade
Life of this patent
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Abstract
An example clock synthesizer, having a single-phase clock signal as input and generating an output clock, includes a phase decrementer configured to receive a fractional period value, configured to, responsive to the fractional period value, maintain a fractional count, and configured to accumulate residual phase from cycle-to-cycle of the output clock. A clock generator provides an integer-count-zero signal indicative of an integer portion of the fractional count reaching zero. A clock phase selector is configured to provide a signal having a fractional portion of the fractional count. A phase generator and combiner is coupled to an output of the clock generator, and an output of the clock phase selector, and is configured to provide the output clock.
Claims20
A clock synthesizer having a single-phase clock signal as input and generating an output clock, the clock synthesizer comprising:
- a phase decrementer having a first input and a second input, the second input configured to receive a fractional period value, the phase decrementer configured to, responsive to the fractional period value, maintain a fractional count and configured to accumulate residual phase from cycle-to-cycle of the output clock;
- a clock generator having an input coupled to a first output of the phase decrementer and an output coupled to the first input of the phase decrementer, the first output of the phase decrementer providing an integer-count-zero signal indicative of an integer portion of the fractional count reaching zero;
- a clock phase selector having an input coupled to a second output of the phase decrementer, the second output of the phase decrementer providing a signal having a fractional portion of the fractional count;
- and
- a phase generator and combiner coupled to an output of the clock generator and an output of the clock phase selector, the phase generator and combiner configured to provide the output clock.
A clock synthesizer having a multi-phase clock signal as input and generating an output clock, the multi-phase clock signal including P clock phases, where P is an integer greater than one, the clock synthesizer comprising:
- a phase decrementer having a first input and a second input, the second input configured to receive a fractional period value, the phase decrementer configured to, responsive to the fractional period value, maintain a fractional count and configured to accumulate residual phase from cycle-to-cycle of the output clock;
- a clock generator having an input coupled to a first output of the phase decrementer and an output coupled to the first input of the phase decrementer, the first output of the phase decrementer providing an integer-count-zero signal indicative of an integer portion of the fractional count reaching zero;
- a clock phase selector having an input coupled to a second output of the phase decrementer, the second output of the phase decrementer providing a signal having a fractional portion of the fractional count, the fractional portion of the fractional count having M bits, where M=log2 (2*P);
- and
- a phase generator and combiner coupled to an output of the clock generator, and a pair of outputs of the clock phase selector, the phase generator and combiner configured to provide the output clock.
A circuit, comprising:
- an analog circuit;
- and
- a clock synthesizer, coupled to the analog circuit to provide an output clock, the clock synthesizer comprising:
- a phase decrementer having a first input and a second input, the second input configured to receive a fractional period value, the phase decrementer configured to, responsive to the fractional period value, maintain a fractional count and configured to accumulate residual phase from cycle-to-cycle of the output clock;
- a clock generator having an input coupled to a first output of the phase decrementer and an output coupled to the first input of the phase decrementer, the first output of the phase decrementer providing an integer-count-zero signal indicative of an integer portion of the fractional count reaching zero;
- a clock phase selector having an input coupled to a second output of the phase decrementer, the second output of the phase decrementer providing a signal having a fractional portion of the fractional count;
- and
- a phase generator and combiner coupled to an output of the clock generator, and at least one output of the clock phase selector, the phase generator and combiner configured to provide the output clock.
Dependencies are inferred from the claim text.