Electronic circuit configured to adjust sampling timing for recovering data
AssigneeSamsung Electronics Co., Ltd.
InventorsKyungho Ryu, Hansu Pae, Kilhoon Lee, Jaeyoul Lee, Jung-Pil Lim, Hyunwook Lim
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Abstract
An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.
Claims19
An electronic circuit comprising:
- a clock recovery circuit configured to generate a first reference clock signal based on first reception data and to generate a second reference clock signal based on second reception data received after the first reception data;
- a sampling clock generator configured to generate a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference signal clock;
- a sampler configured to recover the second reception data based on the generated sampling clock signal;
- and
- a delay locked loop configured to output a first delay clock signal by delaying the first reference clock signal by a reference delay time.
An electronic circuit comprising:
- a clock recovery circuit configured to generate a reference clock signal based on reception data;
- and
- a data recovery circuit configured to recover the reception data based on a sampling clock signal having a phase selected according to a jitter value of the reception data at a recovery point of the reference clock signal;
- wherein, when the jitter value of the reception data exceeds a reference range at the recovery point of the reference clock signal, the data recovery circuit recovers the reception data based on the sampling clock signal having a phase corrected through a comparison with a preset phase.
An electronic circuit comprising:
- a delay locked loop configured to output a first delay clock signal by delaying a first reference clock signal generated based on reception data by a reference delay time;
- a sampling clock generator configured to select a first phase of a first sampling clock signal based on a first phase difference between a second reference clock signal generated based on the reception data and the first delay clock signal;
- and
- a sampler configured to recover the reception data based on the first sampling clock signal having the selected first phase,
- wherein the second reference clock signal is generated after the first reference clock signal is generated.
Dependencies are inferred from the claim text.