Semiconductor device for logic and memory co-optimization
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
Structures and methods for the co-optimization of core (logic) devices and SRAM devices include a semiconductor device having a logic portion and a memory portion. In some embodiments, a logic device is disposed within the logic portion. In some cases, the logic device includes a single fin N-type FinFET and a single fin P-type FinFET. In some examples, a static random-access memory (SRAM) device is disposed within the memory portion. The SRAM device includes an N-well region disposed between two P-well regions, where the two P-well regions include an N-type FinFET pass gate (PG) transistor and an N-type FinFET pull-down (PD) transistor, and where the N-well region includes a P-type FinFET pull-up (PU) transistor.
Claims20
A semiconductor device, comprising:
- a logic portion and a memory portion;
- a logic device disposed within the logic portion, wherein the logic device includes a single fin N-type FinFET and a single fin P-type FinFET;
- and
- a static random-access memory (SRAM) device disposed within the memory portion, wherein the SRAM device includes an N-well region disposed between two P-well regions, wherein the two P-well regions include an N-type FinFET pass gate (PG) transistor and an N-type FinFET pull-down (PD) transistor, and wherein the N-well region includes a P-type FinFET pull-up (PU) transistor;
- wherein a first gate formed over the single fin N-type FinFET has a first end-cap length ‘E1’, and wherein a second gate formed over the N-type FinFET PD transistor has a second end-cap length ‘E2’.
A circuit, comprising:
- a first circuit region and a second circuit region;
- a logic circuit disposed within the first circuit region, wherein the logic circuit includes a double fin N-type FinFET and a double fin P-type FinFET;
- and
- a memory circuit disposed within the second circuit region, wherein the memory circuit includes a first plurality of single fin N-type FinFETs and a second plurality of single fin P-type FinFETs;
- wherein the logic circuit includes a first unit cell having a first X-pitch ‘X1’, wherein the memory circuit includes a second unit cell having a second X-pitch ‘X2’, and wherein the first X-pitch ‘X1’ is the same as the second X-pitch ‘X2’.
A semiconductor device, comprising:
- a plurality of logic portions and a plurality of memory portions disposed on a substrate;
- a plurality of CMOS devices disposed within the plurality of logic portions, wherein each CMOS device includes a single fin N-type FinFET having a first fin width (W1) and a single fin P-type FinFET having a second fin width (W2);
- and
- a plurality of static random-access memory (SRAM) devices disposed within the plurality of memory portions, wherein the plurality of SRAM devices are arranged in a plurality of rows and columns, wherein each SRAM device includes an N-type FinFET pass gate (PG) transistor and an N-type FinFET pull-down (PD) transistor disposed within a P-well region and a P-type FinFET pull-up (PU) transistor disposed within an N-well region, wherein the N-type FinFET PD transistor has a third fin width (W3), wherein the P-type FinFET PU transistor has a fourth fin width (W4) and wherein the first fin width (W1) is narrower than the third fin width (W3);
- wherein a first gate formed over the single fin N-type FinFET has a first end-cap length ‘E1’, wherein the first gate includes a metal gate layer, and wherein the first end-cap length ‘E1’ is at least two times greater than a thickness of the metal gate layer.
Dependencies are inferred from the claim text.