Data retention circuit

A data retention circuit, comprising:

• a first power switch having a first connection terminal coupled to a power voltage, and a second connection terminal, wherein in a sleep mode, the first power switch is turned off and a first leakage current flows between the first connection terminal and the second connection terminal;
• a first inverter having a first input terminal, a first output terminal, and a first power terminal coupled to the second connection terminal, wherein the first inverter comprises a first transistor, and a first terminal of the first transistor is coupled to the first power terminal, and a second terminal of the first transistor is coupled to the first output terminal, wherein in the sleep mode, the first transistor is turned off and a second leakage current flows between the first power terminal and the first output terminal;
• and
• a second inverter having a second input terminal coupled to the first output terminal, a second output terminal coupled to the first input terminal, and a second power terminal coupled to the second connection terminal;
• wherein the first leakage current and the second leakage current form a steady-state voltage on the second connection terminal, and the steady-state voltage is higher than or equal to a data retention voltage.