Current mode logic buffer device for suppressing electromagnetic interference and signal generating method thereof

A current mode logic buffer device for suppressing electromagnetic interference, comprising:

• a first current mode logic buffer having two first input ports, the first current mode logic buffer generating a first clock signal in response to a first differential input signal received by the two first input ports;
• a second current mode logic buffer having two second input ports, the second current mode logic buffer generating a second clock signal in response to a second differential input signal received by the two second input ports, and the second differential input signal being delayed by a time difference from the first differential input signal;
• a third current mode logic buffer having two third input ports, the third current mode logic buffer generating a third clock signal in response to a third differential input signal received by the two third input ports, and the third differential input signal being delayed by the time difference from the second differential input signal;
• and
• two output ports, receiving the first clock signal, the second clock signal, and the third clock signal and outputting a full clock signal;
• wherein the first current mode logic buffer comprises:
• two first load resistors separately connected to a voltage supply terminal;
• two first transistors, a drain of each of the first transistors being separately connected to one of the first load resistors and one of the output ports, and a gate of each of the first transistors being separately connected to one of the first input ports;
• and
• a first current source connected to sources of the two first transistors to provide a first bias current;
• wherein the second current mode logic buffer comprises:
• two second load resistors separately connected to the voltage supply terminal;
• two second transistors, a drain of each of the second transistors being separately connected to one of the second load resistors and one of the output ports, and a gate of each of the second transistors being separately connected to one of the second input ports;
• and
• a second current source connected to sources of the two second transistors to provide a second bias current;
• and
• wherein the third current mode logic buffer comprises:
• two third load resistors separately connected to the voltage supply terminal;
• two third transistors, a drain of each of the third transistors being separately connected to one of the third load resistors and one of the output ports, and a gate of each of the third transistors being separately connected to one of the third input ports;
• and
• a third current source connected to sources of the two third transistors to provide a third bias current.