High voltage tolerant receiver

A circuit comprising:

• a first plurality of transistors configured and arranged as diodes connected in series and coupled between an input terminal and an output terminal, each transistor of the first plurality having a body electrode coupled to a first voltage supply terminal;
• a second plurality of transistors configured and arranged as diodes connected in series and coupled between the output terminal and the first voltage supply terminal;
• a first transistor of the first plurality having a first current electrode and a control electrode coupled at the input terminal, the first transistor configured and arranged for receiving a signal at the input terminal having a voltage exceeding a voltage rating of the first transistor;
• a second transistor having a first current electrode coupled to the first current electrode and the control electrode of the first transistor at the input terminal and a control electrode coupled to a voltage source terminal;
• a third transistor having a first current electrode coupled to a second current electrode of the second transistor at a first node;
• and
• a fourth transistor having a first current electrode coupled to a second current electrode of the third transistor and a second current electrode coupled at the output terminal.

A circuit comprising:

• a first plurality of transistors configured and arranged as diodes connected in series and coupled between an input terminal and an output terminal, each transistor of the first plurality having a body electrode coupled to a first voltage supply terminal;
• a second plurality of transistors configured and arranged as diodes connected in series and coupled between the output terminal and the first voltage supply terminal, each transistor of the second plurality including a first current electrode connected to its control electrode and a second current electrode connected to its body electrode;
• a first transistor of the first plurality having a first current electrode and a control electrode coupled at the input terminal, the first transistor configured and arranged for receiving a signal at the input terminal having a voltage exceeding a voltage rating of the first transistor;
• a second transistor having a first current electrode coupled to the first current electrode and the control electrode of the first transistor at the input terminal and a control electrode coupled to a voltage source terminal;
• a third transistor having a first current electrode coupled to a second current electrode of the second transistor at a first node;
• and
• a fourth transistor having a first current electrode coupled to a second current electrode of the third transistor and a second current electrode coupled at the output terminal.