High voltage interface circuit

A circuit comprising:

• a high voltage (HV) transmission gate comprising a first HV transistor and a second HV transistor coupled in parallel, the HV transmission gate configured and arranged to be non-conductive between a first port and a second port when a control signal is at a first state and conductive between the first port and the second port when the control signal is at a second state;
• a low voltage (LV) circuit coupled to the first port of the HV transmission gate;
• an HV pad coupled to the second port of the HV transmission gate, an operating voltage range of the HV pad having a voltage exceeding an operating voltage rating of an LV transistor in the LV circuit;
• and
• a first secondary electrostatic discharge (SESD) protection device coupled at the second port of the HV transmission gate.

A circuit comprising:

• a high voltage (HV) transmission gate comprising a first HV transistor and a second HV transistor coupled in parallel, the HV transmission gate configured and arranged to be non-conductive between a first port and a second port when a control signal is at a first state and conductive between the first port and the second port when the control signal is at a second state;
• a low voltage (LV) circuit coupled to the first port of the HV transmission gate;
• an ESD resistor having a first terminal coupled to the second port of the HV transmission gate;
• a HV pad coupled to a second terminal of the ESD resistor, an operating voltage range of the HV pad having a voltage exceeding an operating voltage rating of an LV transistor in the LV circuit;
• and
• a secondary electrostatic discharge (SESD) protection device coupled at the second port of the HV transmission gate.