High voltage tolerant analog switch

A circuit comprising:

• a first branch coupled between an input terminal and an output terminal;
• a second branch coupled in parallel with the first branch, the second branch and the first branch configured and arranged to form an analog switch, the analog switch closed when a control signal is at a first state and open when the control signal is at a second state;
• a first transistor in the first branch having a first current electrode coupled at the input terminal, the first transistor configured and arranged for receiving an analog signal at the input terminal having a voltage exceeding a voltage rating of the first transistor;
• a second transistor in the second branch having a first current electrode coupled at the output terminal and a control electrode coupled to receive the control signal, the second transistor configured to be conductive when the control signal is at the first state;
• a first level shifter having an output coupled to a control electrode of the first transistor, the first level shifter configured and arranged to provide a first voltage sufficient to cause the first transistor to be conductive without exceeding the voltage rating when the control signal is at the first state;
• and
• a first voltage generation circuit coupled to the first level shifter, the first voltage generation circuit configured and arranged to generate at a first output the first voltage based on the analog signal and to generate at a second output a second voltage based on the analog signal, the second voltage higher than the first voltage.

A circuit comprising:

• a first branch coupled between an input terminal and an output terminal;
• a first transistor in the first branch having a first current electrode coupled at the input terminal, the first transistor configured and arranged for receiving an input signal at the input terminal having a voltage exceeding a voltage rating of the first transistor;
• a second transistor in the first branch having a first current electrode coupled to a second current electrode of the first transistor at a first node and a second current electrode coupled at the output terminal;
• a third transistor having a first current electrode coupled at the first node and a second electrode coupled to receive a bias voltage;
• and
• a first level shifter having an output coupled to a control electrode of the first transistor, the first level shifter configured and arranged to provide a first voltage when a control signal is at a first state and a second voltage when the control signal is at a second state, the first voltage sufficient to cause the first transistor to be conductive without exceeding the voltage rating of the first transistor and the second voltage sufficient to cause the first transistor to be non-conductive.

A circuit comprising:

• a first branch coupled between an input terminal and an output terminal;
• a second branch coupled in parallel with the first branch, the second branch and the first branch configured and arranged to form an analog switch, the analog switch closed when a control signal is at a first state and open when the control signal is at a second state;
• a first transistor in the first branch having a first current electrode coupled at the input terminal, the first transistor configured and arranged for receiving an analog signal at the input terminal having a voltage exceeding a voltage rating of the first transistor;
• a second transistor in the second branch having a first current electrode coupled at the output terminal and a control electrode coupled to receive the control signal, the second transistor configured to be conductive when the control signal is at the first state;
• a third transistor having a first current electrode coupled to a second current electrode of the first transistor at a first node and a second electrode coupled to receive a bias voltage;
• a fourth transistor having a first current electrode coupled to a second current electrode of the second transistor at a second node and a control electrode coupled to receive the bias voltage;
• and
• a first level shifter having an output coupled to a control electrode of the first transistor, the first level shifter configured and arranged to provide a first voltage sufficient to cause the first transistor to be conductive without exceeding the voltage rating when the control signal is at the first state.

A circuit comprising:

• a first branch coupled between an input terminal and an output terminal;
• a first transistor in the first branch having a first current electrode coupled at the input terminal, the first transistor configured and arranged for receiving an input signal at the input terminal having a voltage exceeding a voltage rating of the first transistor;
• a second transistor in the first branch having a first current electrode coupled to a second current electrode of the first transistor at a first node and a second current electrode coupled at the output terminal;
• and
• a first level shifter having an output coupled to a control electrode of the first transistor, the first level shifter configured and arranged to provide a first voltage when a control signal is at a first state and a second voltage when the control signal is at a second state, the first voltage sufficient to cause the first transistor to be conductive without exceeding the voltage rating of the first transistor and the second voltage sufficient to cause the first transistor to be non-conductive;
• and
• a first voltage generation circuit coupled to the first level shifter, the first voltage generation circuit configured and arranged to generate at a first output the first voltage based on the input signal and at a second output the second voltage based on the input signal, the second voltage higher than the first voltage.