US 10,763,839 B2Granted

Buffer Circuit

AssigneeTexas Instruments Incorporated

InventorsRajat Chauhan, Srikanth Srinivasan

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Abstract

Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node.

Claims13

Dependent claims

A circuit, comprising:

a first diode having a first terminal coupled to a first node and a second terminal;
a second diode coupled in series between the second terminal of the first diode and a second node;
a comparator, comprising:
a comparator first arm including a first plurality of transistor devices, the comparator first arm coupled to the second node and a third node;
a comparator second arm including a second plurality of transistor devices, the comparator second arm coupled to the third node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices;
and
an inverter having an input coupled to the comparator and an output coupled to a fourth node
a level shifter having a first input coupled to the second node, a second input coupled to the fourth node, a third input coupled to a fifth node, and an output;
a buffer having an input coupled to the fifth node and an output;
a first p-type transistor having a gate terminal coupled to the output of the level shifter, a source terminal coupled to the first node, and a drain terminal coupled to a sixth node;
and
a first n-type transistor having a gate terminal coupled to the output of the buffer, a source terminal coupled to a seventh node, and a drain terminal coupled to an eighth node.

9 more elements

A circuit, comprising:

a signal generator, comprising:
a semiconductor device configured to:
receive an input voltage (VIN);
and
generate a reference voltage (VREF) based on a difference between VIN and a threshold voltage;
and
a comparator coupled to an inverter and configured to generate a control signal (LMODE) according to VREF with respect to zero;
and
a level shifter coupled to the signal generator and configured to:
generate an output signal having a value within a range having a lower bound of zero volts and an upper bound of VIN when LMODE is being asserted;
and
generate the output signal having a value within a range having a lower bound of VREF plus the threshold voltage of the semiconductor device and an upper bound of VIN when LMODE is not being asserted.

9 more elements

A system, comprising:

a battery;
a load coupled to the battery and configured to receive an input voltage (VIN) from the battery;
and
a supply voltage supervisor (SVS) coupled to the battery and the load, the SVS comprising an output buffer that comprises:
a signal generator configured to:
receive VIN and generate a reference voltage (VREF) according to VIN minus a threshold voltage of a semiconductor device;
and
generate a control signal (LMODE) according to a value of VREF with respect to zero;
and
a level shifter coupled to the signal generator and configured to:
generate an output signal having a value within a range having a lower bound of zero volts and an upper bound of VIN when LMODE has a first logical value;
and
generate the output signal having a value within a range having a lower bound of VREF plus the threshold voltage of the semiconductor device and an upper bound of VIN when LMODE has a second logical value.

10 more elements

Dependencies are inferred from the claim text.