US 10,763,833 B2Granted

Multiphase oscillator circuit

AssigneeTexas Instruments Incorporated

InventorsErnst Gerog Muellner, Tobias Fritz, Bradley Kramer, Swaminathan Sankaran, Baher Haroun, Ralf Brederlow

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Abstract

In described examples, a ring oscillator includes a series of N stages in a first ring. Each stage includes a respective output terminal coupled to a respective input terminal of a next one of the stages in the first ring. N is a positive odd-numbered integer of at least three. A series of N level shifters in a second ring are respectively connected to the N stages. Each level shifter receives a respective clock output from a respective output terminal of a stage to which it is connected and generates a respective boosted clock output in response thereto. The boosted clock output is coupled to control an impedance state of a next one of the level shifters in the second ring.

Claims19

Dependent claims

A circuit, comprising:

a ring oscillator including a series of N stages in a first ring, each stage including a respective output terminal coupled to a respective input terminal of a next one of the stages in the first ring, wherein N is a positive odd-numbered integer of at least three;
a series of N level shifters in a second ring, respectively connected to the N stages, each level shifter configured to receive a respective clock signal from the respective output terminal of the stage to which it is connected and to generate a respective boosted clock signal responsive thereto, the boosted clock signal controlling an impedance state of a next one of the level shifters in the second ring;
a controller having a control output coupled to at least one of the stages, the controller configured to drive the control output to enable or disable the ring oscillator for a number of pulse edges of the boosted clock signals;
and
a filtering circuit configured to filter one or more of the pulse edges to achieve a particular startup frequency before the control output enables the ring oscillator.

2 more elements

A circuit, comprising:

a ring oscillator including a series of N stages in a first ring, each stage including a respective output terminal coupled to a respective input terminal of a next one of the stages in the first ring, wherein N is a positive odd-numbered integer of at least three;
a series of N level shifters in a second ring, respectively connected to the N stages, each level shifter configured to receive a respective clock signal from the respective output terminal of the stage to which it is connected and to generate a respective boosted clock signal responsive thereto, the boosted clock signal controlling an impedance state of a next one of the level shifters in the second ring;
and
a capacitor and diode network coupled to an input supply voltage terminal, the capacitor and diode network configured to control a startup of the ring oscillator;
in which the stages are coupled to the input supply voltage terminal, the level shifters are coupled to an output supply voltage terminal having a greater voltage than the input supply voltage terminal, and the level shifters are configured to receive the respective clock signals at a voltage level of the input supply voltage terminal and to generate the respective boosted clock signals at a voltage level of the output supply voltage terminal.

2 more elements

A circuit, comprising:

a ring oscillator including a series of stages;
and
first and second level shifters, the first level shifter including first, second and third transistors having respective first, second and third gates, wherein:
the first transistor is coupled between a voltage reference terminal and the second transistor;
the second transistor is coupled between the first and third transistors;
the third transistor is coupled between the second transistor and an input supply voltage terminal;
at the first gate, the first level shifter is coupled to a stage output of one of the stages of the ring oscillator;
the first level shifter is configured to generate a first boosted output at a connection between the second and third transistors, responsive to:
the stage outputs;
and a second boosted output from the second level shifter;
the second and third gates are coupled to the second boosted output and configured to control an impedance state of the first level shifter responsive thereto;
the stages are coupled to the input supply voltage terminal;
the first level shifter is coupled to an output supply voltage terminal having a greater voltage than the input supply voltage terminal;
and
the stage output has a voltage level of the input supply voltage terminal, and the first boosted output has a voltage level of the output supply voltage terminal.

12 more elements

Dependencies are inferred from the claim text.