Generation of pulse width modulated (PWM) pulses

A system-on-chip (SoC), comprising:

• a central processing unit (CPU) core;
• and
• a pulse width modulation (PWM) generator, the PWM generator configured to:
• receive a configuration parameter from the CPU core to generate a pulse having a specified pulse width;
• generate M clocks from N input clocks, M and N are integers, M is greater than N, and each of the M clocks has a frequency that is lower than a frequency of each of the N input clocks;
• generate a plurality of phase-shifted signals, each of the phase-shifted signals generated using a different one of the M clocks;
• and
• assert a control signal to select at least one of the generated phase-shifted signals to generate an output pulse having the specified width.

A circuit, comprising:

• a base pulse generator to generate a first pulse width modulated (PWM) pulse;
• a ring oscillator to generate M clocks of a first frequency;
• a second clock generation circuit to receive the M clocks and to generate N clocks each at a second frequency, the second frequency is lower than the first frequency, wherein N and M are integers and N is greater than M;
• N flip-flops, each of the N flip-flops includes respective a clock input coupled to receive a different one of the N clocks, a respective data input coupled to receive the first PWM pulse, and a respective flip-flop output;
• and
• a first multiplexer including N inputs, each of the N inputs is coupled to a corresponding flip-flop output;
• and
• a second multiplexer coupled to receive an output from the first multiplexer and the first PWM pulse;
• wherein the base pulse generator is configured to assert control signals to the first and second multiplexers.

A method, comprising:

• generating a first pulse width modulated (PWM) pulse;
• generating M clocks of a first frequency, wherein M is an integer;
• using the M clocks, generating N clocks, the N clocks are at a second frequency, lower than the first frequency, wherein N is and integer and is greater than M;
• selecting, by a selection circuit, an output of N flip-flops, each flip-flop including a respective clock input coupled to receive a different one of the N clocks and including a respective data input coupled to receive the first PWM pulse.