Semiconductor device and power converter
AssigneeMitsubishi Electric Corporation
InventorHidenori Fujii
Life of this patent
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Abstract
Provided is a technique for preventing a peak current during recovery while enhancing breakdown voltage. A semiconductor device includes the following: a p−-type anode layer having a uniform p-type impurity concentration; an n−-type layer having a distributed n-type impurity concentration; and an n+-type layer disposed with the n−-type layer interposed between the n+-type layer and the p−-type anode layer, the n+-type layer having an n-type impurity concentration that is higher than that of the n−-type layer and is uniform. The n-type impurity concentration of the n−-type layer in a portion on the p−-type-anode-layer side is lower than the p-type impurity concentration of the p−-type anode layer.
Claims12
A semiconductor device comprising:
- an anode layer having a p-type impurity concentration that is uniform;
- a first semiconductor layer having an n-type impurity concentration that is distributed;
- and
- a second semiconductor layer disposed with the first semiconductor layer interposed between the second semiconductor layer and the anode layer, the second semiconductor layer having an n-type impurity concentration that is higher than that of the first semiconductor layer and is uniform, wherein
- the n-type impurity concentration of the first semiconductor layer in a portion on an anode-layer side is lower than the p-type impurity concentration of the anode layer, and
- the anode layer and the first semiconductor layer form a pn junction closer to a center of the semiconductor device than to an anode layer side of the semiconductor device.
A semiconductor device comprising:
- an anode layer having a p-type impurity concentration that is uniform;
- a first semiconductor layer having an n-type impurity concentration that is distributed;
- and
- a second semiconductor layer disposed with the first semiconductor layer interposed between the second semiconductor layer and the anode layer, the second semiconductor layer having an n-type impurity concentration that is higher than that of the first semiconductor layer and is uniform, wherein
- the n-type impurity concentration of the first semiconductor layer in a portion on an anode-layer side is lower than the p-type impurity concentration of the anode layer, and
- the p-type impurity concentration of the anode layer is 1×1012 cm−3 to 1×1014 cm−3.
Dependencies are inferred from the claim text.