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US 10,763,436 B2Granted
Semiconductor patterning
AssigneeFlexenable Limited
InventorElizabeth Speechley
Life of this patent
Estimating the term…
Abstract
A technique, comprising: forming a stack comprising a semiconductor layer for providing the semiconductor channels of one or more transistors, and an insulator layer; and patterning the stack so as to form in a single process both: (i) one or more interconnection holes for connecting a conductor level on one side of the stack to a conductor level on the opposite side of the stack; and (ii) one or more leakage reduction trenches for reducing leakage paths via the semiconductor between conductor elements on one side of the stack.
Claims9
A method, comprising:
- forming a stack comprising a semiconductor layer for providing the semiconductor channels of one or more transistors, and an insulator layer;
- patterning the stack so as to form in a single process both:
- (i) one or more interconnection holes for connecting a conductor level on one side of the stack to a conductor level on the opposite side of the stack;
- and
- (ii) one or more leakage reduction trenches for reducing leakage paths via the semiconductor between conductor elements on one side of the stack;
- and
- depositing conductor material over the patterned stack, and patterning the conductor material so as to remove the conductor material from the whole of the regions of the one or more leakage reduction trenches, without removing the conductor material in the region of the one or more interconnection holes.
4 more elements
Dependencies are inferred from the claim text.