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US 10,763,432 B2Granted
Chalcogenide-based memory architecture
AssigneeIntel Corporation
InventorMario Allegra
Life of this patent
Estimating the term…
Abstract
A memory cell can include a chalcogenide material configured in an annular shape or a chalcogenide material substantially circumscribing an interior conductive channel. Such memory cells can be included in memory structures having an interior conductive channel and a plurality of alternating dielectric layers and memory layers oriented along the interior conductive channel. Individual memory layers can include a chalcogenide material substantially circumscribing the interior conductive channel.
Claims27
A memory cell, comprising:
- a chalcogenide memory element configured in an annular shape and located between adjacent dielectric layers;
- an interior electrode material configured in an annular shape, wherein the interior electrode material is substantially circumscribed by the chalcogenide memory element and located between the adjacent dielectric layers;
- and
- an interior conductive material configured as a wordline or a bitline.
1 more element
A memory device, comprising:
- an array of memory structures, comprising:
- a plurality of interior conductive channels configured as individual wordlines or individual bitlines,
- a plurality of first level memory cells within a first memory layer, individual first level memory cells comprising a first chalcogenide memory element disposed about individual interior conductive channels at the first memory layer and located between adjacent dielectric layers, and
- a plurality of second level memory cells within a second memory layer, individual second level memory cells comprising a second chalcogenide memory element disposed about individual interior conductive channels at the second memory layer and located between adjacent dielectric layers,
- wherein individual memory cells in the first memory layer and the second memory layer further comprise an interior electrode material between the first chalcogenide memory element in the first memory layer and the second chalcogenide memory element in the second memory layer and the interior conductive channel;
- a first level decoder electrically coupled in a first direction to first level memory cells;
- and
- a second level decoder electrically coupled in a second direction to second level memory cells.
5 more elements
Dependencies are inferred from the claim text.