Film stress control for memory device stack

A semiconductor structure comprising:

• a bottom electrode located on a surface of a first electrically conductive structure, wherein the first electrically conductive structure is embedded in a first interconnect dielectric material layer;
• a first compressive metal-containing portion located above the bottom electrode;
• a memory device pillar located on a surface of the first compressive metal-containing portion, wherein the memory device pillar is a ferroelectric memory (FE) device pillar, a resistive random access memory (ReRAM) device pillar, a magnetoresistive random access memory (MRAM) device pillar, or a phase change random access memory (PRAM) device pillar;
• and
• a top electrode composed of a first tensile metal-containing portion located on the memory device pillar.

A method of reducing wafer bowing in a semiconductor structure, the method comprising:

• forming a bottom electrode located on a surface of a first electrically conductive structure, wherein the first electrically conductive structure is embedded in a first interconnect dielectric material layer;
• forming a memory device stack above the bottom electrode and on a topmost surface of the first interconnect dielectric material layer, wherein a first compressive metal-containing layer contacts one surface of the memory device stack and the memory device stack is a ferroelectric memory (FE) device stack, a resistive random access memory (ReRAM) device stack, a magnetoresistive random access memory (MRAM) device stack, or a phase change random access memory (PRAM) device stack;
• and
• forming a first tensile metal-containing layer above the memory device stack, wherein the first tensile metal-containing layer compensates the compressive stress caused by the first compressive metal-containing layer.