# US 10,763,429 B2 · Self-aligned ion beam etch sputter mask for magnetoresistive random access memory

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,763,429 B2
- Document ID: US10763429B2
- Status: Granted
- Kind: B2
- Application number: 16/158,791
- Filed: 2018-10-12
- Published: 2020-04-16
- Granted: 2020-09-01
- Earliest claimed: 2018-10-12
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Steve Holmes; Bruce B. Doris; Hyun K. Lee
- Web page: https://patentgrep.com/patent/US10763429B2

## CPC

- H10N 50/01: Manufacture or treatment
- H10B 61/20: {comprising components having three or more electrodes, e.g. transistors}
- H10N 50/10: Magnetoresistive devices
- H10N 50/85: Materials of the active region
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Embodiments of the present invention are directed to a method for fabricating a magnetoresistive random access memory (MRAM) device. A non-limiting example of the method includes depositing a dielectric layer on a contact arranged on a substrate including a magnetic tunnel junction (MTJ) pillar. The method includes reducing a width of the MTJ pillar. The method further includes depositing an encapsulation layer on the dielectric layer and the MTJ pillar.

## Claims

### Claim 1

A method of fabricating a magnetoresistive random access memory (MRAM) device, the method comprising:
depositing a dielectric layer on a contact arranged on a substrate comprising a magnetic tunnel junction (MTJ) pillar;
reducing a width of the MTJ pillar; and
depositing an encapsulation layer on the dielectric layer and the MTJ pillar;
wherein reducing the width of the MTJ pillar causes a portion of the dielectric layer to redeposit onto a vertical sidewall of the MTJ pillar.

### Claim 2 (depends on 1)

The method of claim 1, wherein the MTJ pillar is arranged directly on the contact.

### Claim 3 (depends on 1)

The method of claim 1, wherein the dielectric layer is not deposited on the vertical sidewalls of the MTJ pillar.

### Claim 4 (depends on 1)

The method of claim 1, wherein reducing the width of the MTJ pillar comprises ion beam etching.

### Claim 5 (depends on 1)

The method of claim 1, wherein the dielectric layer and the encapsulation layer comprise different dielectric materials.

### Claim 6 (depends on 1)

The method of claim 1, wherein the dielectric layer and the encapsulation layer comprise the same dielectric materials.

### Claim 7

A method of fabricating a magnetoresistive random access memory (MRAM) device, the method comprising:
depositing, by spin coating, a dielectric layer on a contact arranged on a substrate comprising a magnetic tunnel junction (MTJ) pillar;
reducing a width of the MTJ pillar to form a gap between a vertical sidewall of the MTJ pillar and the dielectric layer; and
depositing an encapsulation layer on the dielectric layer and the MTJ pillar.

### Claim 8 (depends on 7)

The method of claim 7, wherein the dielectric layer is not deposited on the vertical sidewalls of the MTJ pillar.

### Claim 9 (depends on 7)

The method of claim 7, wherein reducing the width of the MTJ pillar comprises ion beam etching.

### Claim 10 (depends on 7)

The method of claim 7, wherein reducing the width of the MTJ pillar causes a portion of the dielectric layer to redeposit onto a vertical sidewall of the MTJ pillar.

### Claim 11 (depends on 7)

The method of claim 7, wherein the dielectric layer and the encapsulation layer comprise different dielectric materials.

### Claim 12 (depends on 7)

The method of claim 7, wherein the dielectric layer and the encapsulation layer comprise the same dielectric materials.