Method for forming a flat bottom electrode via (BEVA) top surface for memory

A method for forming an integrated circuit, the method comprising:

• patterning a first dielectric layer to form a first opening overlying and exposing a first conductive wire that underlies the first dielectric layer;
• forming a lower via structure partially filling the first opening and having a top surface that is uneven and is fully recessed relative to a top surface of the first dielectric layer;
• depositing a first metal layer covering the first dielectric layer and filling a remainder of the first opening over the lower via structure;
• performing a first planarization into the first metal layer until a top surface of the first metal layer is about even with the top surface of the first dielectric layer, wherein the first planarization forms an upper via structure on the lower via structure;
• and
• forming a memory cell on the upper via structure and the first dielectric layer.

A method for forming an integrated circuit, the method comprising:

• patterning a first dielectric layer to form a first opening overlying and exposing a first conductive wire that underlies the first dielectric layer;
• depositing a conductive barrier layer covering the first dielectric layer and partially filling the first opening;
• depositing a first metal layer covering the conductive barrier layer and filling a remainder of the first opening over the conductive barrier layer;
• simultaneously etching back a top surface of the first metal layer and a top surface of the conductive barrier layer to below a top surface of the first dielectric layer, wherein the etching back clears a portion of the first opening;
• forming a second metal layer filling the portion of the first opening and having a top surface that is about even with the top surface of the first dielectric layer;
• and
• forming a memory cell overlying the first conductive wire on the second metal layer.