# US 10,763,420 B2 · Josephson Junction damascene fabrication > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,763,420 B2 - Document ID: US10763420B2 - Status: Granted - Kind: B2 - Application number: 16/301,498 - Filed: 2016-06-13 - Published: 2019-09-26 - Granted: 2020-09-01 - Earliest claimed: 2016-06-13 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Zachary R. Yoscovits; David J. Michalak; Jeanette M. Roberts; Ravi Pillarisetty; James S. Clarke - Web page: https://patentgrep.com/patent/US10763420B2 ## CPC - H10N 60/0912: {of Josephson-effect devices} - H10N 60/01: Manufacture or treatment - H10N 60/12: Josephson-effect devices - H10N 60/805: {for Josephson-effect devices} - H10N 60/83: Element shape - H10N 60/85: Superconducting active materials - H10N 69/00: Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00 - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that can be efficiently used in large scale manufacturing, providing a substantial improvement with respect to conventional approaches which include fabrications steps which are not manufacturable. In one aspect of the present disclosure, the proposed approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer. The proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ. ## Claims ### Claim 1 A superconducting qubit for a quantum circuit provided over a substrate, the superconducting qubit comprising: a Josephson Junction provided over the substrate, the Josephson Junction comprising a base electrode layer, a top electrode layer, and a tunnel barrier layer provided between the base electrode layer and the top electrode layer, wherein the Josephson Junction is provided in a via opening provided over the substrate, and the via opening is surrounded by a dielectric. ### Claim 2 (depends on 1) The superconducting qubit according to claim 1, wherein the thickness of the base electrode layer is less than 5 nm. ### Claim 3 (depends on 1) The superconducting qubit according to claim 1, wherein an upper surface of the dielectric is aligned with an upper surface of the top electrode layer. ### Claim 4 (depends on 1) The superconducting qubit according to claim 1, wherein the via opening is substantially perpendicular to the substrate. ### Claim 5 (depends on 1) The superconducting qubit according to claim 1, wherein the base electrode layer is provided on a patterned superconductor layer provided over the substrate, and wherein dimensions of the base electrode layer in a plane of the base electrode layer and the patterned superconductor layer are smaller than dimensions of the patterned superconductor layer. ### Claim 6 (depends on 1) The superconducting qubit according to claim 1, further comprising an interconnect configured to provide electrical interconnection between the top electrode layer and a further component of the quantum circuit. ### Claim 7 (depends on 6) The superconducting qubit according to claim 6, wherein the interconnect comprises a first portion provided in a plane substantially parallel to a plane of the substrate, and wherein a part of the first portion is in contact with the top electrode layer. ### Claim 8 (depends on 6) The superconducting qubit according to claim 6, wherein the further component of the quantum circuit comprises a SQUID loop. ### Claim 9 (depends on 6) The superconducting qubit according to claim 6, wherein the further component of the quantum circuit comprises a capacitor of the superconducting qubit. ### Claim 10 (depends on 1) The superconducting qubit according to claim 1, wherein the superconducting qubit is a charge qubit. ### Claim 11 (depends on 1) The superconducting qubit according to claim 1, wherein the superconducting qubit is a transmon. ### Claim 12 (depends on 1) The superconducting qubit according to claim 1, wherein the superconducting qubit is a flux qubit. ### Claim 13 A quantum integrated circuit package, comprising: a substrate; and a first superconducting qubit and a second superconducting qubit provided over the substrate, wherein each of the first superconducting qubit and the second superconducting qubit comprises a Josephson Junction comprising a base electrode layer, a top electrode layer, and a tunnel barrier layer provided between the base electrode layer and the top electrode layer, wherein the Josephson Junction is provided in a via opening provided over the substrate, and the via opening is surrounded by a dielectric. ### Claim 14 (depends on 13) The quantum integrated circuit package according to claim 13, wherein the first superconducting qubit and the second superconducting qubit are coupled by a coupling resonator. ### Claim 15 A quantum computing device, comprising: a package substrate; and a first superconducting qubit and a second superconducting qubit provided over the package substrate, wherein each of the first superconducting qubit and the second superconducting qubit comprises a Josephson Junction comprising a base electrode layer, a top electrode layer, and a tunnel barrier layer provided between the base electrode layer and the top electrode layer, wherein the Josephson Junction is provided in a via opening provided over the substrate, and the via opening is surrounded by a dielectric. ### Claim 16 (depends on 15) The quantum computing device according to claim 15, further comprising a cryogenic apparatus configured to maintain the first superconducting qubit and the second superconducting qubit at a cryogenic temperature during operation of the first superconducting qubit and the second superconducting qubit.