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US 10,763,368 B2Granted
Stacked gate-all-around FinFET and method forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
Life of this patent
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Abstract
A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.
Claims20
A method comprising:
- forming a semiconductor stack comprising a first plurality of semiconductor layers and a second plurality of semiconductor layers laid out alternatingly;
- patterning the semiconductor stack to form a stack of semiconductor strips;
- removing the second plurality of semiconductor layers in the stack of semiconductor strips, with the first plurality of semiconductor layers in the stack of semiconductor strip remaining as semiconductor strips, wherein the removing the second plurality of semiconductor layers comprises:
- oxidizing the second plurality of semiconductor layers partially to form oxide regions;
- etching the oxide regions;
- and
- after the oxide regions are etched, etching remaining portions of the second plurality of semiconductor layers;
- and
- forming gate dielectrics on the semiconductor strips, with each of the gate dielectrics encircling ones of the semiconductor strips.
6 more elements
A method comprising:
- forming a semiconductor strip stack;
- removing a portion of the semiconductor strip stack to form:
- a first semiconductor strip;
- and
- a second semiconductor strip overlapping the first semiconductor strip, wherein the first semiconductor strip and the second semiconductor strip are spaced apart by a space;
- forming a silicon germanium oxide region overlapped by the first semiconductor strip;
- forming isolation regions having opposing portions on opposite sides of the silicon germanium oxide region, wherein the silicon germanium oxide region is embedded in the isolation regions;
- forming gate dielectrics surrounding the first semiconductor strip and the second semiconductor strip, wherein a portion of the gate dielectrics directly underlying the first semiconductor strip has a top surface contacting the first semiconductor strip, and a bottom surface contacting the silicon germanium oxide region;
- and
- forming a source region and a drain region, wherein the source region and the drain region are electrically coupled to each other by the first semiconductor strip and the second semiconductor strip.
7 more elements
A method comprising:
- depositing a silicon germanium layer over a semiconductor substrate;
- depositing a semiconductor stack over the silicon germanium layer, wherein the semiconductor stack comprises:
- a first plurality of semiconductor layers formed of a first semiconductor material;
- and
- a second plurality of semiconductor layers formed of a second semiconductor material different from the first semiconductor material, wherein the first plurality of semiconductor layers and the second plurality of semiconductor layers are stacked alternatingly;
- etching the silicon germanium layer, the semiconductor stack and the semiconductor substrate to form a strip stack, wherein remaining portions of the first and the second semiconductor layers form first semiconductor strips and second semiconductor strips, respectively, in the strip stack, and a remaining portion of the silicon germanium layer forms a silicon germanium strip;
- filling a dielectric material into trenches that are generated by the etching to form isolation regions;
- recessing the isolation regions to reveal the first semiconductor strips and the second semiconductor strips;
- performing an oxidation process to fully oxidize the silicon germanium strip to generate a first silicon germanium oxide region, and in the oxidation process, the first semiconductor strips is partially oxidized to form second silicon germanium oxide regions;
- and
- removing the first semiconductor strips.
8 more elements
Dependencies are inferred from the claim text.