Metal rail conductors for non-planar semiconductor devices

An integrated circuit, comprising:

• a dielectric region;
• and
• a first fin field-effect transistor (finFET), including a first source region, a first gate region, and a first drain region situated onto the dielectric region and a first fin structure protruding from the dielectric region;
• a second finFET including a second source region, a second gate region, and a second drain region situated onto the dielectric region and a second fin structure protruding from the dielectric region;
• a first rail conductor situated within the dielectric region, the first rail conductor being electrically connected to the first gate region and the second gate region;
• a seed layer under the first rail conductor;
• and
• a second rail conductor situated within the dielectric region, the second rail conductor being electrically connected to the first source region and the second source region.

A fin field-effect transistor (finFET) array, comprising:

• a semiconductor substrate;
• a dielectric region situated above the semiconductor substrate;
• a plurality of source regions situated onto the dielectric region;
• a plurality of gate regions situated onto the dielectric region;
• a plurality of drain regions situated onto the dielectric region;
• a fin structure situated onto the semiconductor substrate and traversing through the dielectric region, the fin structure being configured to be between the plurality of source regions and the plurality of drain regions and to traverse through the plurality of gate regions;
• a first rail conductor situated within the dielectric region, wherein the first rail conductor is arranged to be:
• electrically connected to a first terminal region selected from among the plurality of source regions, the plurality of gate regions, and plurality of the drain regions, and
• in parallel with the fin structure and to extend a horizontal length of the semiconductor substrate;
• a seed layer between the first rail conductor and the semiconductor substrate;
• and
• a second rail conductor situated within the dielectric region, wherein the second rail conductor is electrically connected to a second terminal region selected from among the plurality of source regions, the plurality of gate regions, and plurality of the drain regions.