# US 10,763,360 B2 · Ferroelectric memory device and method of manufacturing the same

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- Number: US 10,763,360 B2
- Document ID: US10763360B2
- Status: Granted
- Kind: B2
- Application number: 15/868,583
- Filed: 2018-01-11
- Published: 2018-10-04
- Granted: 2020-09-01
- Earliest claimed: 2017-03-31
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hyangkeun Yoo
- Web page: https://patentgrep.com/patent/US10763360B2

## CPC

- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/689: {having ferroelectric layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A ferroelectric memory device includes a substrate having a source region and a drain region, a first ferroelectric material layer and a second ferroelectric material layer sequentially stacked on the substrate, and a gate electrode layer disposed on the second ferroelectric material layer. The second ferroelectric material layer has an oxygen vacancy concentration different from that of the first ferroelectric material layer.

## Claims

### Claim 1

A ferroelectric memory device comprising:
a substrate having a source region and a drain region;
a first ferroelectric material layer and a second ferroelectric material layer that are sequentially stacked on the substrate; and
a gate electrode layer disposed on the second ferroelectric material layer,
wherein the second ferroelectric material layer has a higher oxygen vacancy concentration than that of the first ferroelectric material layer,
wherein a work function of the gate electrode layer is greater than an electron affinity of the second ferroelectric material layer.

### Claim 2 (depends on 1)

The ferroelectric memory device of claim 1, wherein at least one of the first ferroelectric material layer and the second ferroelectric material layer comprises a dopant, and
the dopant comprises at least one selected from carbon, silicon, magnesium, aluminum, yttrium, nitrogen, germanium, tin, strontium, lead, calcium, barium, titanium, zirconium, gadolinium, and lanthanum.

### Claim 3 (depends on 1)

The ferroelectric memory device of claim 1, wherein the gate electrode layer comprises at least one selected from tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

### Claim 4 (depends on 1)

The ferroelectric memory device of claim 1, wherein a sum of the thickness of the first ferroelectric material layer and the thickness of the second ferroelectric material layer is 4 nm to 10 nm.

### Claim 5 (depends on 4)

The ferroelectric memory device of claim 4, wherein a ratio of the thickness of the first ferroelectric material layer and the thickness of the second ferroelectric material layer is 8:1 to 4:1.

### Claim 6 (depends on 1)

The ferroelectric memory device of claim 1, further comprising
a gate insulation layer disposed between the substrate and the first ferroelectric material layer.

### Claim 7 (depends on 1)

The ferroelectric memory device of claim 1, wherein each of the first and second ferroelectric material layers comprises at least one of hafnium oxide and zirconium oxide.

### Claim 8 (depends on 7)

The ferroelectric memory device of claim 7, wherein the gate electrode layer comprises at least one selected from tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

### Claim 9 (depends on 8)

The ferroelectric memory device of claim 8, further comprising an interfacial insulation layer disposed between the second ferroelectric material layer and the gate electrode layer.